1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2018 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 12*4882a593Smuzhiyun * all copies or substantial portions of the Software. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun #ifndef __AMDGPU_CTX_H__ 24*4882a593Smuzhiyun #define __AMDGPU_CTX_H__ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #include "amdgpu_ring.h" 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun struct drm_device; 29*4882a593Smuzhiyun struct drm_file; 30*4882a593Smuzhiyun struct amdgpu_fpriv; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define AMDGPU_MAX_ENTITY_NUM 4 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun struct amdgpu_ctx_entity { 35*4882a593Smuzhiyun uint64_t sequence; 36*4882a593Smuzhiyun struct drm_sched_entity entity; 37*4882a593Smuzhiyun struct dma_fence *fences[]; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun struct amdgpu_ctx { 41*4882a593Smuzhiyun struct kref refcount; 42*4882a593Smuzhiyun struct amdgpu_device *adev; 43*4882a593Smuzhiyun unsigned reset_counter; 44*4882a593Smuzhiyun unsigned reset_counter_query; 45*4882a593Smuzhiyun uint32_t vram_lost_counter; 46*4882a593Smuzhiyun spinlock_t ring_lock; 47*4882a593Smuzhiyun struct amdgpu_ctx_entity *entities[AMDGPU_HW_IP_NUM][AMDGPU_MAX_ENTITY_NUM]; 48*4882a593Smuzhiyun bool preamble_presented; 49*4882a593Smuzhiyun enum drm_sched_priority init_priority; 50*4882a593Smuzhiyun enum drm_sched_priority override_priority; 51*4882a593Smuzhiyun struct mutex lock; 52*4882a593Smuzhiyun atomic_t guilty; 53*4882a593Smuzhiyun unsigned long ras_counter_ce; 54*4882a593Smuzhiyun unsigned long ras_counter_ue; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun struct amdgpu_ctx_mgr { 58*4882a593Smuzhiyun struct amdgpu_device *adev; 59*4882a593Smuzhiyun struct mutex lock; 60*4882a593Smuzhiyun /* protected by lock */ 61*4882a593Smuzhiyun struct idr ctx_handles; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun extern const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM]; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); 67*4882a593Smuzhiyun int amdgpu_ctx_put(struct amdgpu_ctx *ctx); 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun int amdgpu_ctx_get_entity(struct amdgpu_ctx *ctx, u32 hw_ip, u32 instance, 70*4882a593Smuzhiyun u32 ring, struct drm_sched_entity **entity); 71*4882a593Smuzhiyun void amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, 72*4882a593Smuzhiyun struct drm_sched_entity *entity, 73*4882a593Smuzhiyun struct dma_fence *fence, uint64_t *seq); 74*4882a593Smuzhiyun struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 75*4882a593Smuzhiyun struct drm_sched_entity *entity, 76*4882a593Smuzhiyun uint64_t seq); 77*4882a593Smuzhiyun void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx, 78*4882a593Smuzhiyun enum drm_sched_priority priority); 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 81*4882a593Smuzhiyun struct drm_file *filp); 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, 84*4882a593Smuzhiyun struct drm_sched_entity *entity); 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); 87*4882a593Smuzhiyun void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr); 88*4882a593Smuzhiyun long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout); 89*4882a593Smuzhiyun void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #endif 92