xref: /OK3568_Linux_fs/kernel/drivers/gpu/arm/bifrost/mali_kbase_pbha.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * (C) COPYRIGHT 2021-2022 ARM Limited. All rights reserved.
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * This program is free software and is provided to you under the terms of the
7*4882a593Smuzhiyun  * GNU General Public License version 2 as published by the Free Software
8*4882a593Smuzhiyun  * Foundation, and any use by you of this program is subject to the terms
9*4882a593Smuzhiyun  * of such GNU license.
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * This program is distributed in the hope that it will be useful,
12*4882a593Smuzhiyun  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13*4882a593Smuzhiyun  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14*4882a593Smuzhiyun  * GNU General Public License for more details.
15*4882a593Smuzhiyun  *
16*4882a593Smuzhiyun  * You should have received a copy of the GNU General Public License
17*4882a593Smuzhiyun  * along with this program; if not, you can access it online at
18*4882a593Smuzhiyun  * http://www.gnu.org/licenses/gpl-2.0.html.
19*4882a593Smuzhiyun  *
20*4882a593Smuzhiyun  */
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #include "mali_kbase_pbha.h"
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun #include <device/mali_kbase_device.h>
25*4882a593Smuzhiyun #include <mali_kbase.h>
26*4882a593Smuzhiyun #define DTB_SET_SIZE 2
27*4882a593Smuzhiyun 
read_setting_valid(unsigned int id,unsigned int read_setting)28*4882a593Smuzhiyun static bool read_setting_valid(unsigned int id, unsigned int read_setting)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun 	switch (id) {
31*4882a593Smuzhiyun 	/* Valid ID - fall through all */
32*4882a593Smuzhiyun 	case SYSC_ALLOC_ID_R_OTHER:
33*4882a593Smuzhiyun 	case SYSC_ALLOC_ID_R_CSF:
34*4882a593Smuzhiyun 	case SYSC_ALLOC_ID_R_MMU:
35*4882a593Smuzhiyun 	case SYSC_ALLOC_ID_R_TILER_VERT:
36*4882a593Smuzhiyun 	case SYSC_ALLOC_ID_R_TILER_PTR:
37*4882a593Smuzhiyun 	case SYSC_ALLOC_ID_R_TILER_INDEX:
38*4882a593Smuzhiyun 	case SYSC_ALLOC_ID_R_TILER_OTHER:
39*4882a593Smuzhiyun 	case SYSC_ALLOC_ID_R_IC:
40*4882a593Smuzhiyun 	case SYSC_ALLOC_ID_R_ATTR:
41*4882a593Smuzhiyun 	case SYSC_ALLOC_ID_R_SCM:
42*4882a593Smuzhiyun 	case SYSC_ALLOC_ID_R_FSDC:
43*4882a593Smuzhiyun 	case SYSC_ALLOC_ID_R_VL:
44*4882a593Smuzhiyun 	case SYSC_ALLOC_ID_R_PLR:
45*4882a593Smuzhiyun 	case SYSC_ALLOC_ID_R_TEX:
46*4882a593Smuzhiyun 	case SYSC_ALLOC_ID_R_LSC:
47*4882a593Smuzhiyun 		switch (read_setting) {
48*4882a593Smuzhiyun 		/* Valid setting value - fall through all */
49*4882a593Smuzhiyun 		case SYSC_ALLOC_L2_ALLOC:
50*4882a593Smuzhiyun 		case SYSC_ALLOC_NEVER_ALLOC:
51*4882a593Smuzhiyun 		case SYSC_ALLOC_ALWAYS_ALLOC:
52*4882a593Smuzhiyun 		case SYSC_ALLOC_PTL_ALLOC:
53*4882a593Smuzhiyun 		case SYSC_ALLOC_L2_PTL_ALLOC:
54*4882a593Smuzhiyun 			return true;
55*4882a593Smuzhiyun 		default:
56*4882a593Smuzhiyun 			return false;
57*4882a593Smuzhiyun 		}
58*4882a593Smuzhiyun 	default:
59*4882a593Smuzhiyun 		return false;
60*4882a593Smuzhiyun 	}
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 	/* Unreachable */
63*4882a593Smuzhiyun 	return false;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun 
write_setting_valid(unsigned int id,unsigned int write_setting)66*4882a593Smuzhiyun static bool write_setting_valid(unsigned int id, unsigned int write_setting)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun 	switch (id) {
69*4882a593Smuzhiyun 	/* Valid ID - fall through all */
70*4882a593Smuzhiyun 	case SYSC_ALLOC_ID_W_OTHER:
71*4882a593Smuzhiyun 	case SYSC_ALLOC_ID_W_CSF:
72*4882a593Smuzhiyun 	case SYSC_ALLOC_ID_W_PCB:
73*4882a593Smuzhiyun 	case SYSC_ALLOC_ID_W_TILER_PTR:
74*4882a593Smuzhiyun 	case SYSC_ALLOC_ID_W_TILER_VERT_PLIST:
75*4882a593Smuzhiyun 	case SYSC_ALLOC_ID_W_TILER_OTHER:
76*4882a593Smuzhiyun 	case SYSC_ALLOC_ID_W_L2_EVICT:
77*4882a593Smuzhiyun 	case SYSC_ALLOC_ID_W_L2_FLUSH:
78*4882a593Smuzhiyun 	case SYSC_ALLOC_ID_W_TIB_COLOR:
79*4882a593Smuzhiyun 	case SYSC_ALLOC_ID_W_TIB_COLOR_AFBCH:
80*4882a593Smuzhiyun 	case SYSC_ALLOC_ID_W_TIB_COLOR_AFBCB:
81*4882a593Smuzhiyun 	case SYSC_ALLOC_ID_W_TIB_CRC:
82*4882a593Smuzhiyun 	case SYSC_ALLOC_ID_W_TIB_DS:
83*4882a593Smuzhiyun 	case SYSC_ALLOC_ID_W_TIB_DS_AFBCH:
84*4882a593Smuzhiyun 	case SYSC_ALLOC_ID_W_TIB_DS_AFBCB:
85*4882a593Smuzhiyun 	case SYSC_ALLOC_ID_W_LSC:
86*4882a593Smuzhiyun 		switch (write_setting) {
87*4882a593Smuzhiyun 		/* Valid setting value - fall through all */
88*4882a593Smuzhiyun 		case SYSC_ALLOC_L2_ALLOC:
89*4882a593Smuzhiyun 		case SYSC_ALLOC_NEVER_ALLOC:
90*4882a593Smuzhiyun 		case SYSC_ALLOC_ALWAYS_ALLOC:
91*4882a593Smuzhiyun 		case SYSC_ALLOC_PTL_ALLOC:
92*4882a593Smuzhiyun 		case SYSC_ALLOC_L2_PTL_ALLOC:
93*4882a593Smuzhiyun 			return true;
94*4882a593Smuzhiyun 		default:
95*4882a593Smuzhiyun 			return false;
96*4882a593Smuzhiyun 		}
97*4882a593Smuzhiyun 	default:
98*4882a593Smuzhiyun 		return false;
99*4882a593Smuzhiyun 	}
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 	/* Unreachable */
102*4882a593Smuzhiyun 	return false;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun /* Private structure to be returned as setting validity status */
106*4882a593Smuzhiyun struct settings_status {
107*4882a593Smuzhiyun 	/* specifies whether id and either one of settings is valid */
108*4882a593Smuzhiyun 	bool overall;
109*4882a593Smuzhiyun 	/* specifies whether read setting is valid */
110*4882a593Smuzhiyun 	bool read;
111*4882a593Smuzhiyun 	/* specifies whether write setting is valid*/
112*4882a593Smuzhiyun 	bool write;
113*4882a593Smuzhiyun };
114*4882a593Smuzhiyun 
settings_valid(unsigned int id,unsigned int read_setting,unsigned int write_setting)115*4882a593Smuzhiyun static struct settings_status settings_valid(unsigned int id, unsigned int read_setting,
116*4882a593Smuzhiyun 					     unsigned int write_setting)
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun 	struct settings_status valid = { .overall = (id < SYSC_ALLOC_COUNT * sizeof(u32)) };
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	if (valid.overall) {
121*4882a593Smuzhiyun 		valid.read = read_setting_valid(id, read_setting);
122*4882a593Smuzhiyun 		valid.write = write_setting_valid(id, write_setting);
123*4882a593Smuzhiyun 		valid.overall = valid.read || valid.write;
124*4882a593Smuzhiyun 	}
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	return valid;
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun 
kbasep_pbha_supported(struct kbase_device * kbdev)129*4882a593Smuzhiyun bool kbasep_pbha_supported(struct kbase_device *kbdev)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun 	const u32 arch_maj_rev =
132*4882a593Smuzhiyun 		ARCH_MAJOR_REV_REG(kbdev->gpu_props.props.raw_props.gpu_id);
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 	return (arch_maj_rev >= GPU_ID2_ARCH_MAJOR_REV_MAKE(11, 3));
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun 
kbase_pbha_record_settings(struct kbase_device * kbdev,bool runtime,unsigned int id,unsigned int read_setting,unsigned int write_setting)137*4882a593Smuzhiyun int kbase_pbha_record_settings(struct kbase_device *kbdev, bool runtime,
138*4882a593Smuzhiyun 			       unsigned int id, unsigned int read_setting,
139*4882a593Smuzhiyun 			       unsigned int write_setting)
140*4882a593Smuzhiyun {
141*4882a593Smuzhiyun 	struct settings_status const valid = settings_valid(id, read_setting, write_setting);
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	if (valid.overall) {
144*4882a593Smuzhiyun 		unsigned int const sysc_alloc_num = id / sizeof(u32);
145*4882a593Smuzhiyun 		u32 modified_reg;
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 		if (runtime) {
148*4882a593Smuzhiyun 			int i;
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 			kbase_pm_context_active(kbdev);
151*4882a593Smuzhiyun 			/* Ensure host copy of SYSC_ALLOC is up to date */
152*4882a593Smuzhiyun 			for (i = 0; i < SYSC_ALLOC_COUNT; i++)
153*4882a593Smuzhiyun 				kbdev->sysc_alloc[i] = kbase_reg_read(
154*4882a593Smuzhiyun 					kbdev, GPU_CONTROL_REG(SYSC_ALLOC(i)));
155*4882a593Smuzhiyun 			kbase_pm_context_idle(kbdev);
156*4882a593Smuzhiyun 		}
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 		modified_reg = kbdev->sysc_alloc[sysc_alloc_num];
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 		switch (id % sizeof(u32)) {
161*4882a593Smuzhiyun 		case 0:
162*4882a593Smuzhiyun 			modified_reg = valid.read ? SYSC_ALLOC_R_SYSC_ALLOC0_SET(modified_reg,
163*4882a593Smuzhiyun 										 read_setting) :
164*4882a593Smuzhiyun 						    modified_reg;
165*4882a593Smuzhiyun 			modified_reg = valid.write ? SYSC_ALLOC_W_SYSC_ALLOC0_SET(modified_reg,
166*4882a593Smuzhiyun 										  write_setting) :
167*4882a593Smuzhiyun 						     modified_reg;
168*4882a593Smuzhiyun 			break;
169*4882a593Smuzhiyun 		case 1:
170*4882a593Smuzhiyun 			modified_reg = valid.read ? SYSC_ALLOC_R_SYSC_ALLOC1_SET(modified_reg,
171*4882a593Smuzhiyun 										 read_setting) :
172*4882a593Smuzhiyun 						    modified_reg;
173*4882a593Smuzhiyun 			modified_reg = valid.write ? SYSC_ALLOC_W_SYSC_ALLOC1_SET(modified_reg,
174*4882a593Smuzhiyun 										  write_setting) :
175*4882a593Smuzhiyun 						     modified_reg;
176*4882a593Smuzhiyun 			break;
177*4882a593Smuzhiyun 		case 2:
178*4882a593Smuzhiyun 			modified_reg = valid.read ? SYSC_ALLOC_R_SYSC_ALLOC2_SET(modified_reg,
179*4882a593Smuzhiyun 										 read_setting) :
180*4882a593Smuzhiyun 						    modified_reg;
181*4882a593Smuzhiyun 			modified_reg = valid.write ? SYSC_ALLOC_W_SYSC_ALLOC2_SET(modified_reg,
182*4882a593Smuzhiyun 										  write_setting) :
183*4882a593Smuzhiyun 						     modified_reg;
184*4882a593Smuzhiyun 			break;
185*4882a593Smuzhiyun 		case 3:
186*4882a593Smuzhiyun 			modified_reg = valid.read ? SYSC_ALLOC_R_SYSC_ALLOC3_SET(modified_reg,
187*4882a593Smuzhiyun 										 read_setting) :
188*4882a593Smuzhiyun 						    modified_reg;
189*4882a593Smuzhiyun 			modified_reg = valid.write ? SYSC_ALLOC_W_SYSC_ALLOC3_SET(modified_reg,
190*4882a593Smuzhiyun 										  write_setting) :
191*4882a593Smuzhiyun 						     modified_reg;
192*4882a593Smuzhiyun 			break;
193*4882a593Smuzhiyun 		}
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 		kbdev->sysc_alloc[sysc_alloc_num] = modified_reg;
196*4882a593Smuzhiyun 	}
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 	return valid.overall ? 0 : -EINVAL;
199*4882a593Smuzhiyun }
200*4882a593Smuzhiyun 
kbase_pbha_write_settings(struct kbase_device * kbdev)201*4882a593Smuzhiyun void kbase_pbha_write_settings(struct kbase_device *kbdev)
202*4882a593Smuzhiyun {
203*4882a593Smuzhiyun 	if (kbasep_pbha_supported(kbdev)) {
204*4882a593Smuzhiyun 		int i;
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun 		for (i = 0; i < SYSC_ALLOC_COUNT; ++i)
207*4882a593Smuzhiyun 			kbase_reg_write(kbdev, GPU_CONTROL_REG(SYSC_ALLOC(i)),
208*4882a593Smuzhiyun 					kbdev->sysc_alloc[i]);
209*4882a593Smuzhiyun 	}
210*4882a593Smuzhiyun }
211*4882a593Smuzhiyun 
kbase_pbha_read_int_id_override_property(struct kbase_device * kbdev,const struct device_node * pbha_node)212*4882a593Smuzhiyun static int kbase_pbha_read_int_id_override_property(struct kbase_device *kbdev,
213*4882a593Smuzhiyun 						    const struct device_node *pbha_node)
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun 	u32 dtb_data[SYSC_ALLOC_COUNT * sizeof(u32) * DTB_SET_SIZE];
216*4882a593Smuzhiyun 	int sz, i;
217*4882a593Smuzhiyun 	bool valid = true;
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun 	sz = of_property_count_elems_of_size(pbha_node, "int_id_override",
220*4882a593Smuzhiyun 					     sizeof(u32));
221*4882a593Smuzhiyun 	if (sz <= 0 || (sz % DTB_SET_SIZE != 0)) {
222*4882a593Smuzhiyun 		dev_err(kbdev->dev, "Bad DTB format: pbha.int_id_override\n");
223*4882a593Smuzhiyun 		return -EINVAL;
224*4882a593Smuzhiyun 	}
225*4882a593Smuzhiyun 	if (of_property_read_u32_array(pbha_node, "int_id_override", dtb_data,
226*4882a593Smuzhiyun 				       sz) != 0) {
227*4882a593Smuzhiyun 		dev_err(kbdev->dev,
228*4882a593Smuzhiyun 			"Failed to read DTB pbha.int_id_override\n");
229*4882a593Smuzhiyun 		return -EINVAL;
230*4882a593Smuzhiyun 	}
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 	for (i = 0; valid && i < sz; i = i + DTB_SET_SIZE) {
233*4882a593Smuzhiyun 		unsigned int rdset =
234*4882a593Smuzhiyun 			SYSC_ALLOC_R_SYSC_ALLOC0_GET(dtb_data[i + 1]);
235*4882a593Smuzhiyun 		unsigned int wrset =
236*4882a593Smuzhiyun 			SYSC_ALLOC_W_SYSC_ALLOC0_GET(dtb_data[i + 1]);
237*4882a593Smuzhiyun 		valid = valid &&
238*4882a593Smuzhiyun 			(kbase_pbha_record_settings(kbdev, false, dtb_data[i],
239*4882a593Smuzhiyun 						    rdset, wrset) == 0);
240*4882a593Smuzhiyun 		if (valid)
241*4882a593Smuzhiyun 			dev_info(kbdev->dev,
242*4882a593Smuzhiyun 				 "pbha.int_id_override 0x%x r0x%x w0x%x\n",
243*4882a593Smuzhiyun 				 dtb_data[i], rdset, wrset);
244*4882a593Smuzhiyun 	}
245*4882a593Smuzhiyun 	if (i != sz || (!valid)) {
246*4882a593Smuzhiyun 		dev_err(kbdev->dev,
247*4882a593Smuzhiyun 			"Failed recording DTB data (pbha.int_id_override)\n");
248*4882a593Smuzhiyun 		return -EINVAL;
249*4882a593Smuzhiyun 	}
250*4882a593Smuzhiyun 	return 0;
251*4882a593Smuzhiyun }
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun #if MALI_USE_CSF
kbase_pbha_read_propagate_bits_property(struct kbase_device * kbdev,const struct device_node * pbha_node)254*4882a593Smuzhiyun static int kbase_pbha_read_propagate_bits_property(struct kbase_device *kbdev,
255*4882a593Smuzhiyun 						   const struct device_node *pbha_node)
256*4882a593Smuzhiyun {
257*4882a593Smuzhiyun 	u32 bits;
258*4882a593Smuzhiyun 	int err;
259*4882a593Smuzhiyun 
260*4882a593Smuzhiyun 	if (!kbase_hw_has_feature(kbdev, BASE_HW_FEATURE_PBHA_HWU))
261*4882a593Smuzhiyun 		return 0;
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun 	err = of_property_read_u32(pbha_node, "propagate_bits", &bits);
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun 	if (err < 0) {
266*4882a593Smuzhiyun 		if (err != -EINVAL) {
267*4882a593Smuzhiyun 			dev_err(kbdev->dev,
268*4882a593Smuzhiyun 				"DTB value for propagate_bits is improperly formed (err=%d)\n",
269*4882a593Smuzhiyun 				err);
270*4882a593Smuzhiyun 			return err;
271*4882a593Smuzhiyun 		}
272*4882a593Smuzhiyun 	}
273*4882a593Smuzhiyun 
274*4882a593Smuzhiyun 	if (bits > (L2_CONFIG_PBHA_HWU_MASK >> L2_CONFIG_PBHA_HWU_SHIFT)) {
275*4882a593Smuzhiyun 		dev_err(kbdev->dev, "Bad DTB value for propagate_bits: 0x%x\n", bits);
276*4882a593Smuzhiyun 		return -EINVAL;
277*4882a593Smuzhiyun 	}
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun 	kbdev->pbha_propagate_bits = bits;
280*4882a593Smuzhiyun 	return 0;
281*4882a593Smuzhiyun }
282*4882a593Smuzhiyun #endif
283*4882a593Smuzhiyun 
kbase_pbha_read_dtb(struct kbase_device * kbdev)284*4882a593Smuzhiyun int kbase_pbha_read_dtb(struct kbase_device *kbdev)
285*4882a593Smuzhiyun {
286*4882a593Smuzhiyun 	const struct device_node *pbha_node;
287*4882a593Smuzhiyun 	int err;
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun 	if (!kbasep_pbha_supported(kbdev))
290*4882a593Smuzhiyun 		return 0;
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun 	pbha_node = of_get_child_by_name(kbdev->dev->of_node, "pbha");
293*4882a593Smuzhiyun 	if (!pbha_node)
294*4882a593Smuzhiyun 		return 0;
295*4882a593Smuzhiyun 
296*4882a593Smuzhiyun 	err = kbase_pbha_read_int_id_override_property(kbdev, pbha_node);
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun #if MALI_USE_CSF
299*4882a593Smuzhiyun 	if (err < 0)
300*4882a593Smuzhiyun 		return err;
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun 	err = kbase_pbha_read_propagate_bits_property(kbdev, pbha_node);
303*4882a593Smuzhiyun #endif
304*4882a593Smuzhiyun 
305*4882a593Smuzhiyun 	return err;
306*4882a593Smuzhiyun }
307