1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * GPIO driver for EXAR XRA1403 16-bit GPIO expander
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2017, General Electric Company
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/bitops.h>
9*4882a593Smuzhiyun #include <linux/gpio/driver.h>
10*4882a593Smuzhiyun #include <linux/kernel.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/mutex.h>
13*4882a593Smuzhiyun #include <linux/of_device.h>
14*4882a593Smuzhiyun #include <linux/of_gpio.h>
15*4882a593Smuzhiyun #include <linux/seq_file.h>
16*4882a593Smuzhiyun #include <linux/spi/spi.h>
17*4882a593Smuzhiyun #include <linux/regmap.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /* XRA1403 registers */
20*4882a593Smuzhiyun #define XRA_GSR 0x00 /* GPIO State */
21*4882a593Smuzhiyun #define XRA_OCR 0x02 /* Output Control */
22*4882a593Smuzhiyun #define XRA_PIR 0x04 /* Input Polarity Inversion */
23*4882a593Smuzhiyun #define XRA_GCR 0x06 /* GPIO Configuration */
24*4882a593Smuzhiyun #define XRA_PUR 0x08 /* Input Internal Pull-up Resistor Enable/Disable */
25*4882a593Smuzhiyun #define XRA_IER 0x0A /* Input Interrupt Enable */
26*4882a593Smuzhiyun #define XRA_TSCR 0x0C /* Output Three-State Control */
27*4882a593Smuzhiyun #define XRA_ISR 0x0E /* Input Interrupt Status */
28*4882a593Smuzhiyun #define XRA_REIR 0x10 /* Input Rising Edge Interrupt Enable */
29*4882a593Smuzhiyun #define XRA_FEIR 0x12 /* Input Falling Edge Interrupt Enable */
30*4882a593Smuzhiyun #define XRA_IFR 0x14 /* Input Filter Enable/Disable */
31*4882a593Smuzhiyun #define XRA_LAST 0x15 /* Bounds */
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun struct xra1403 {
34*4882a593Smuzhiyun struct gpio_chip chip;
35*4882a593Smuzhiyun struct regmap *regmap;
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun static const struct regmap_config xra1403_regmap_cfg = {
39*4882a593Smuzhiyun .reg_bits = 7,
40*4882a593Smuzhiyun .pad_bits = 1,
41*4882a593Smuzhiyun .val_bits = 8,
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun .max_register = XRA_LAST,
44*4882a593Smuzhiyun };
45*4882a593Smuzhiyun
to_reg(unsigned int reg,unsigned int offset)46*4882a593Smuzhiyun static unsigned int to_reg(unsigned int reg, unsigned int offset)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun return reg + (offset > 7);
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
xra1403_direction_input(struct gpio_chip * chip,unsigned int offset)51*4882a593Smuzhiyun static int xra1403_direction_input(struct gpio_chip *chip, unsigned int offset)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun struct xra1403 *xra = gpiochip_get_data(chip);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun return regmap_update_bits(xra->regmap, to_reg(XRA_GCR, offset),
56*4882a593Smuzhiyun BIT(offset % 8), BIT(offset % 8));
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
xra1403_direction_output(struct gpio_chip * chip,unsigned int offset,int value)59*4882a593Smuzhiyun static int xra1403_direction_output(struct gpio_chip *chip, unsigned int offset,
60*4882a593Smuzhiyun int value)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun int ret;
63*4882a593Smuzhiyun struct xra1403 *xra = gpiochip_get_data(chip);
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun ret = regmap_update_bits(xra->regmap, to_reg(XRA_GCR, offset),
66*4882a593Smuzhiyun BIT(offset % 8), 0);
67*4882a593Smuzhiyun if (ret)
68*4882a593Smuzhiyun return ret;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun ret = regmap_update_bits(xra->regmap, to_reg(XRA_OCR, offset),
71*4882a593Smuzhiyun BIT(offset % 8), value ? BIT(offset % 8) : 0);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun return ret;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
xra1403_get_direction(struct gpio_chip * chip,unsigned int offset)76*4882a593Smuzhiyun static int xra1403_get_direction(struct gpio_chip *chip, unsigned int offset)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun int ret;
79*4882a593Smuzhiyun unsigned int val;
80*4882a593Smuzhiyun struct xra1403 *xra = gpiochip_get_data(chip);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun ret = regmap_read(xra->regmap, to_reg(XRA_GCR, offset), &val);
83*4882a593Smuzhiyun if (ret)
84*4882a593Smuzhiyun return ret;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun if (val & BIT(offset % 8))
87*4882a593Smuzhiyun return GPIO_LINE_DIRECTION_IN;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun return GPIO_LINE_DIRECTION_OUT;
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
xra1403_get(struct gpio_chip * chip,unsigned int offset)92*4882a593Smuzhiyun static int xra1403_get(struct gpio_chip *chip, unsigned int offset)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun int ret;
95*4882a593Smuzhiyun unsigned int val;
96*4882a593Smuzhiyun struct xra1403 *xra = gpiochip_get_data(chip);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun ret = regmap_read(xra->regmap, to_reg(XRA_GSR, offset), &val);
99*4882a593Smuzhiyun if (ret)
100*4882a593Smuzhiyun return ret;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun return !!(val & BIT(offset % 8));
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
xra1403_set(struct gpio_chip * chip,unsigned int offset,int value)105*4882a593Smuzhiyun static void xra1403_set(struct gpio_chip *chip, unsigned int offset, int value)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun int ret;
108*4882a593Smuzhiyun struct xra1403 *xra = gpiochip_get_data(chip);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun ret = regmap_update_bits(xra->regmap, to_reg(XRA_OCR, offset),
111*4882a593Smuzhiyun BIT(offset % 8), value ? BIT(offset % 8) : 0);
112*4882a593Smuzhiyun if (ret)
113*4882a593Smuzhiyun dev_err(chip->parent, "Failed to set pin: %d, ret: %d\n",
114*4882a593Smuzhiyun offset, ret);
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun #ifdef CONFIG_DEBUG_FS
xra1403_dbg_show(struct seq_file * s,struct gpio_chip * chip)118*4882a593Smuzhiyun static void xra1403_dbg_show(struct seq_file *s, struct gpio_chip *chip)
119*4882a593Smuzhiyun {
120*4882a593Smuzhiyun int reg;
121*4882a593Smuzhiyun struct xra1403 *xra = gpiochip_get_data(chip);
122*4882a593Smuzhiyun int value[XRA_LAST];
123*4882a593Smuzhiyun int i;
124*4882a593Smuzhiyun const char *label;
125*4882a593Smuzhiyun unsigned int gcr;
126*4882a593Smuzhiyun unsigned int gsr;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun seq_puts(s, "xra reg:");
129*4882a593Smuzhiyun for (reg = 0; reg <= XRA_LAST; reg++)
130*4882a593Smuzhiyun seq_printf(s, " %2.2x", reg);
131*4882a593Smuzhiyun seq_puts(s, "\n value:");
132*4882a593Smuzhiyun for (reg = 0; reg < XRA_LAST; reg++) {
133*4882a593Smuzhiyun regmap_read(xra->regmap, reg, &value[reg]);
134*4882a593Smuzhiyun seq_printf(s, " %2.2x", value[reg]);
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun seq_puts(s, "\n");
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun gcr = value[XRA_GCR + 1] << 8 | value[XRA_GCR];
139*4882a593Smuzhiyun gsr = value[XRA_GSR + 1] << 8 | value[XRA_GSR];
140*4882a593Smuzhiyun for_each_requested_gpio(chip, i, label) {
141*4882a593Smuzhiyun seq_printf(s, " gpio-%-3d (%-12s) %s %s\n",
142*4882a593Smuzhiyun chip->base + i, label,
143*4882a593Smuzhiyun (gcr & BIT(i)) ? "in" : "out",
144*4882a593Smuzhiyun (gsr & BIT(i)) ? "hi" : "lo");
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun #else
148*4882a593Smuzhiyun #define xra1403_dbg_show NULL
149*4882a593Smuzhiyun #endif
150*4882a593Smuzhiyun
xra1403_probe(struct spi_device * spi)151*4882a593Smuzhiyun static int xra1403_probe(struct spi_device *spi)
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun struct xra1403 *xra;
154*4882a593Smuzhiyun struct gpio_desc *reset_gpio;
155*4882a593Smuzhiyun int ret;
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun xra = devm_kzalloc(&spi->dev, sizeof(*xra), GFP_KERNEL);
158*4882a593Smuzhiyun if (!xra)
159*4882a593Smuzhiyun return -ENOMEM;
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun /* bring the chip out of reset if reset pin is provided*/
162*4882a593Smuzhiyun reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset", GPIOD_OUT_LOW);
163*4882a593Smuzhiyun if (IS_ERR(reset_gpio))
164*4882a593Smuzhiyun dev_warn(&spi->dev, "Could not get reset-gpios\n");
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun xra->chip.direction_input = xra1403_direction_input;
167*4882a593Smuzhiyun xra->chip.direction_output = xra1403_direction_output;
168*4882a593Smuzhiyun xra->chip.get_direction = xra1403_get_direction;
169*4882a593Smuzhiyun xra->chip.get = xra1403_get;
170*4882a593Smuzhiyun xra->chip.set = xra1403_set;
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun xra->chip.dbg_show = xra1403_dbg_show;
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun xra->chip.ngpio = 16;
175*4882a593Smuzhiyun xra->chip.label = "xra1403";
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun xra->chip.base = -1;
178*4882a593Smuzhiyun xra->chip.can_sleep = true;
179*4882a593Smuzhiyun xra->chip.parent = &spi->dev;
180*4882a593Smuzhiyun xra->chip.owner = THIS_MODULE;
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun xra->regmap = devm_regmap_init_spi(spi, &xra1403_regmap_cfg);
183*4882a593Smuzhiyun if (IS_ERR(xra->regmap)) {
184*4882a593Smuzhiyun ret = PTR_ERR(xra->regmap);
185*4882a593Smuzhiyun dev_err(&spi->dev, "Failed to allocate regmap: %d\n", ret);
186*4882a593Smuzhiyun return ret;
187*4882a593Smuzhiyun }
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun ret = devm_gpiochip_add_data(&spi->dev, &xra->chip, xra);
190*4882a593Smuzhiyun if (ret < 0) {
191*4882a593Smuzhiyun dev_err(&spi->dev, "Unable to register gpiochip\n");
192*4882a593Smuzhiyun return ret;
193*4882a593Smuzhiyun }
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun spi_set_drvdata(spi, xra);
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun return 0;
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun static const struct spi_device_id xra1403_ids[] = {
201*4882a593Smuzhiyun { "xra1403" },
202*4882a593Smuzhiyun {},
203*4882a593Smuzhiyun };
204*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, xra1403_ids);
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun static const struct of_device_id xra1403_spi_of_match[] = {
207*4882a593Smuzhiyun { .compatible = "exar,xra1403" },
208*4882a593Smuzhiyun {},
209*4882a593Smuzhiyun };
210*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, xra1403_spi_of_match);
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun static struct spi_driver xra1403_driver = {
213*4882a593Smuzhiyun .probe = xra1403_probe,
214*4882a593Smuzhiyun .id_table = xra1403_ids,
215*4882a593Smuzhiyun .driver = {
216*4882a593Smuzhiyun .name = "xra1403",
217*4882a593Smuzhiyun .of_match_table = of_match_ptr(xra1403_spi_of_match),
218*4882a593Smuzhiyun },
219*4882a593Smuzhiyun };
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun module_spi_driver(xra1403_driver);
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun MODULE_AUTHOR("Nandor Han <nandor.han@ge.com>");
224*4882a593Smuzhiyun MODULE_AUTHOR("Semi Malinen <semi.malinen@ge.com>");
225*4882a593Smuzhiyun MODULE_DESCRIPTION("GPIO expander driver for EXAR XRA1403");
226*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
227