xref: /OK3568_Linux_fs/kernel/drivers/gpio/gpio-twl4030.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Access to GPIOs on TWL4030/TPS659x0 chips
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2006-2007 Texas Instruments, Inc.
6*4882a593Smuzhiyun  * Copyright (C) 2006 MontaVista Software, Inc.
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * Code re-arranged and cleaned up by:
9*4882a593Smuzhiyun  *	Syed Mohammed Khasim <x0khasim@ti.com>
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * Initial Code:
12*4882a593Smuzhiyun  *	Andy Lowe / Nishanth Menon
13*4882a593Smuzhiyun  */
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #include <linux/module.h>
16*4882a593Smuzhiyun #include <linux/init.h>
17*4882a593Smuzhiyun #include <linux/interrupt.h>
18*4882a593Smuzhiyun #include <linux/kthread.h>
19*4882a593Smuzhiyun #include <linux/irq.h>
20*4882a593Smuzhiyun #include <linux/gpio/driver.h>
21*4882a593Smuzhiyun #include <linux/platform_device.h>
22*4882a593Smuzhiyun #include <linux/of.h>
23*4882a593Smuzhiyun #include <linux/irqdomain.h>
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #include <linux/mfd/twl.h>
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun /*
28*4882a593Smuzhiyun  * The GPIO "subchip" supports 18 GPIOs which can be configured as
29*4882a593Smuzhiyun  * inputs or outputs, with pullups or pulldowns on each pin.  Each
30*4882a593Smuzhiyun  * GPIO can trigger interrupts on either or both edges.
31*4882a593Smuzhiyun  *
32*4882a593Smuzhiyun  * GPIO interrupts can be fed to either of two IRQ lines; this is
33*4882a593Smuzhiyun  * intended to support multiple hosts.
34*4882a593Smuzhiyun  *
35*4882a593Smuzhiyun  * There are also two LED pins used sometimes as output-only GPIOs.
36*4882a593Smuzhiyun  */
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun /* genirq interfaces are not available to modules */
39*4882a593Smuzhiyun #ifdef MODULE
40*4882a593Smuzhiyun #define is_module()	true
41*4882a593Smuzhiyun #else
42*4882a593Smuzhiyun #define is_module()	false
43*4882a593Smuzhiyun #endif
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun /* GPIO_CTRL Fields */
46*4882a593Smuzhiyun #define MASK_GPIO_CTRL_GPIO0CD1		BIT(0)
47*4882a593Smuzhiyun #define MASK_GPIO_CTRL_GPIO1CD2		BIT(1)
48*4882a593Smuzhiyun #define MASK_GPIO_CTRL_GPIO_ON		BIT(2)
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun /* Mask for GPIO registers when aggregated into a 32-bit integer */
51*4882a593Smuzhiyun #define GPIO_32_MASK			0x0003ffff
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun struct gpio_twl4030_priv {
54*4882a593Smuzhiyun 	struct gpio_chip gpio_chip;
55*4882a593Smuzhiyun 	struct mutex mutex;
56*4882a593Smuzhiyun 	int irq_base;
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun 	/* Bitfields for state caching */
59*4882a593Smuzhiyun 	unsigned int usage_count;
60*4882a593Smuzhiyun 	unsigned int direction;
61*4882a593Smuzhiyun 	unsigned int out_state;
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun /*----------------------------------------------------------------------*/
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun /*
67*4882a593Smuzhiyun  * To configure TWL4030 GPIO module registers
68*4882a593Smuzhiyun  */
gpio_twl4030_write(u8 address,u8 data)69*4882a593Smuzhiyun static inline int gpio_twl4030_write(u8 address, u8 data)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun 	return twl_i2c_write_u8(TWL4030_MODULE_GPIO, data, address);
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun /*----------------------------------------------------------------------*/
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun /*
77*4882a593Smuzhiyun  * LED register offsets from TWL_MODULE_LED base
78*4882a593Smuzhiyun  * PWMs A and B are dedicated to LEDs A and B, respectively.
79*4882a593Smuzhiyun  */
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun #define TWL4030_LED_LEDEN_REG	0x00
82*4882a593Smuzhiyun #define TWL4030_PWMAON_REG	0x01
83*4882a593Smuzhiyun #define TWL4030_PWMAOFF_REG	0x02
84*4882a593Smuzhiyun #define TWL4030_PWMBON_REG	0x03
85*4882a593Smuzhiyun #define TWL4030_PWMBOFF_REG	0x04
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun /* LEDEN bits */
88*4882a593Smuzhiyun #define LEDEN_LEDAON		BIT(0)
89*4882a593Smuzhiyun #define LEDEN_LEDBON		BIT(1)
90*4882a593Smuzhiyun #define LEDEN_LEDAEXT		BIT(2)
91*4882a593Smuzhiyun #define LEDEN_LEDBEXT		BIT(3)
92*4882a593Smuzhiyun #define LEDEN_LEDAPWM		BIT(4)
93*4882a593Smuzhiyun #define LEDEN_LEDBPWM		BIT(5)
94*4882a593Smuzhiyun #define LEDEN_PWM_LENGTHA	BIT(6)
95*4882a593Smuzhiyun #define LEDEN_PWM_LENGTHB	BIT(7)
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun #define PWMxON_LENGTH		BIT(7)
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun /*----------------------------------------------------------------------*/
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun /*
102*4882a593Smuzhiyun  * To read a TWL4030 GPIO module register
103*4882a593Smuzhiyun  */
gpio_twl4030_read(u8 address)104*4882a593Smuzhiyun static inline int gpio_twl4030_read(u8 address)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun 	u8 data;
107*4882a593Smuzhiyun 	int ret = 0;
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun 	ret = twl_i2c_read_u8(TWL4030_MODULE_GPIO, &data, address);
110*4882a593Smuzhiyun 	return (ret < 0) ? ret : data;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun /*----------------------------------------------------------------------*/
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun static u8 cached_leden;
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun /* The LED lines are open drain outputs ... a FET pulls to GND, so an
118*4882a593Smuzhiyun  * external pullup is needed.  We could also expose the integrated PWM
119*4882a593Smuzhiyun  * as a LED brightness control; we initialize it as "always on".
120*4882a593Smuzhiyun  */
twl4030_led_set_value(int led,int value)121*4882a593Smuzhiyun static void twl4030_led_set_value(int led, int value)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun 	u8 mask = LEDEN_LEDAON | LEDEN_LEDAPWM;
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	if (led)
126*4882a593Smuzhiyun 		mask <<= 1;
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	if (value)
129*4882a593Smuzhiyun 		cached_leden &= ~mask;
130*4882a593Smuzhiyun 	else
131*4882a593Smuzhiyun 		cached_leden |= mask;
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	WARN_ON_ONCE(twl_i2c_write_u8(TWL4030_MODULE_LED, cached_leden,
134*4882a593Smuzhiyun 				      TWL4030_LED_LEDEN_REG));
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun 
twl4030_set_gpio_direction(int gpio,int is_input)137*4882a593Smuzhiyun static int twl4030_set_gpio_direction(int gpio, int is_input)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun 	u8 d_bnk = gpio >> 3;
140*4882a593Smuzhiyun 	u8 d_msk = BIT(gpio & 0x7);
141*4882a593Smuzhiyun 	u8 reg = 0;
142*4882a593Smuzhiyun 	u8 base = REG_GPIODATADIR1 + d_bnk;
143*4882a593Smuzhiyun 	int ret = 0;
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun 	ret = gpio_twl4030_read(base);
146*4882a593Smuzhiyun 	if (ret >= 0) {
147*4882a593Smuzhiyun 		if (is_input)
148*4882a593Smuzhiyun 			reg = ret & ~d_msk;
149*4882a593Smuzhiyun 		else
150*4882a593Smuzhiyun 			reg = ret | d_msk;
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 		ret = gpio_twl4030_write(base, reg);
153*4882a593Smuzhiyun 	}
154*4882a593Smuzhiyun 	return ret;
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun 
twl4030_get_gpio_direction(int gpio)157*4882a593Smuzhiyun static int twl4030_get_gpio_direction(int gpio)
158*4882a593Smuzhiyun {
159*4882a593Smuzhiyun 	u8 d_bnk = gpio >> 3;
160*4882a593Smuzhiyun 	u8 d_msk = BIT(gpio & 0x7);
161*4882a593Smuzhiyun 	u8 base = REG_GPIODATADIR1 + d_bnk;
162*4882a593Smuzhiyun 	int ret = 0;
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	ret = gpio_twl4030_read(base);
165*4882a593Smuzhiyun 	if (ret < 0)
166*4882a593Smuzhiyun 		return ret;
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun 	if (ret & d_msk)
169*4882a593Smuzhiyun 		return GPIO_LINE_DIRECTION_OUT;
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun 	return GPIO_LINE_DIRECTION_IN;
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun 
twl4030_set_gpio_dataout(int gpio,int enable)174*4882a593Smuzhiyun static int twl4030_set_gpio_dataout(int gpio, int enable)
175*4882a593Smuzhiyun {
176*4882a593Smuzhiyun 	u8 d_bnk = gpio >> 3;
177*4882a593Smuzhiyun 	u8 d_msk = BIT(gpio & 0x7);
178*4882a593Smuzhiyun 	u8 base = 0;
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	if (enable)
181*4882a593Smuzhiyun 		base = REG_SETGPIODATAOUT1 + d_bnk;
182*4882a593Smuzhiyun 	else
183*4882a593Smuzhiyun 		base = REG_CLEARGPIODATAOUT1 + d_bnk;
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 	return gpio_twl4030_write(base, d_msk);
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun 
twl4030_get_gpio_datain(int gpio)188*4882a593Smuzhiyun static int twl4030_get_gpio_datain(int gpio)
189*4882a593Smuzhiyun {
190*4882a593Smuzhiyun 	u8 d_bnk = gpio >> 3;
191*4882a593Smuzhiyun 	u8 d_off = gpio & 0x7;
192*4882a593Smuzhiyun 	u8 base = 0;
193*4882a593Smuzhiyun 	int ret = 0;
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 	base = REG_GPIODATAIN1 + d_bnk;
196*4882a593Smuzhiyun 	ret = gpio_twl4030_read(base);
197*4882a593Smuzhiyun 	if (ret > 0)
198*4882a593Smuzhiyun 		ret = (ret >> d_off) & 0x1;
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	return ret;
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun /*----------------------------------------------------------------------*/
204*4882a593Smuzhiyun 
twl_request(struct gpio_chip * chip,unsigned offset)205*4882a593Smuzhiyun static int twl_request(struct gpio_chip *chip, unsigned offset)
206*4882a593Smuzhiyun {
207*4882a593Smuzhiyun 	struct gpio_twl4030_priv *priv = gpiochip_get_data(chip);
208*4882a593Smuzhiyun 	int status = 0;
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun 	mutex_lock(&priv->mutex);
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun 	/* Support the two LED outputs as output-only GPIOs. */
213*4882a593Smuzhiyun 	if (offset >= TWL4030_GPIO_MAX) {
214*4882a593Smuzhiyun 		u8	ledclr_mask = LEDEN_LEDAON | LEDEN_LEDAEXT
215*4882a593Smuzhiyun 				| LEDEN_LEDAPWM | LEDEN_PWM_LENGTHA;
216*4882a593Smuzhiyun 		u8	reg = TWL4030_PWMAON_REG;
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun 		offset -= TWL4030_GPIO_MAX;
219*4882a593Smuzhiyun 		if (offset) {
220*4882a593Smuzhiyun 			ledclr_mask <<= 1;
221*4882a593Smuzhiyun 			reg = TWL4030_PWMBON_REG;
222*4882a593Smuzhiyun 		}
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun 		/* initialize PWM to always-drive */
225*4882a593Smuzhiyun 		/* Configure PWM OFF register first */
226*4882a593Smuzhiyun 		status = twl_i2c_write_u8(TWL4030_MODULE_LED, 0x7f, reg + 1);
227*4882a593Smuzhiyun 		if (status < 0)
228*4882a593Smuzhiyun 			goto done;
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun 		/* Followed by PWM ON register */
231*4882a593Smuzhiyun 		status = twl_i2c_write_u8(TWL4030_MODULE_LED, 0x7f, reg);
232*4882a593Smuzhiyun 		if (status < 0)
233*4882a593Smuzhiyun 			goto done;
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun 		/* init LED to not-driven (high) */
236*4882a593Smuzhiyun 		status = twl_i2c_read_u8(TWL4030_MODULE_LED, &cached_leden,
237*4882a593Smuzhiyun 					 TWL4030_LED_LEDEN_REG);
238*4882a593Smuzhiyun 		if (status < 0)
239*4882a593Smuzhiyun 			goto done;
240*4882a593Smuzhiyun 		cached_leden &= ~ledclr_mask;
241*4882a593Smuzhiyun 		status = twl_i2c_write_u8(TWL4030_MODULE_LED, cached_leden,
242*4882a593Smuzhiyun 					  TWL4030_LED_LEDEN_REG);
243*4882a593Smuzhiyun 		if (status < 0)
244*4882a593Smuzhiyun 			goto done;
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun 		status = 0;
247*4882a593Smuzhiyun 		goto done;
248*4882a593Smuzhiyun 	}
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun 	/* on first use, turn GPIO module "on" */
251*4882a593Smuzhiyun 	if (!priv->usage_count) {
252*4882a593Smuzhiyun 		struct twl4030_gpio_platform_data *pdata;
253*4882a593Smuzhiyun 		u8 value = MASK_GPIO_CTRL_GPIO_ON;
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun 		/* optionally have the first two GPIOs switch vMMC1
256*4882a593Smuzhiyun 		 * and vMMC2 power supplies based on card presence.
257*4882a593Smuzhiyun 		 */
258*4882a593Smuzhiyun 		pdata = dev_get_platdata(chip->parent);
259*4882a593Smuzhiyun 		if (pdata)
260*4882a593Smuzhiyun 			value |= pdata->mmc_cd & 0x03;
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun 		status = gpio_twl4030_write(REG_GPIO_CTRL, value);
263*4882a593Smuzhiyun 	}
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun done:
266*4882a593Smuzhiyun 	if (!status)
267*4882a593Smuzhiyun 		priv->usage_count |= BIT(offset);
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun 	mutex_unlock(&priv->mutex);
270*4882a593Smuzhiyun 	return status;
271*4882a593Smuzhiyun }
272*4882a593Smuzhiyun 
twl_free(struct gpio_chip * chip,unsigned offset)273*4882a593Smuzhiyun static void twl_free(struct gpio_chip *chip, unsigned offset)
274*4882a593Smuzhiyun {
275*4882a593Smuzhiyun 	struct gpio_twl4030_priv *priv = gpiochip_get_data(chip);
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun 	mutex_lock(&priv->mutex);
278*4882a593Smuzhiyun 	if (offset >= TWL4030_GPIO_MAX) {
279*4882a593Smuzhiyun 		twl4030_led_set_value(offset - TWL4030_GPIO_MAX, 1);
280*4882a593Smuzhiyun 		goto out;
281*4882a593Smuzhiyun 	}
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun 	priv->usage_count &= ~BIT(offset);
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun 	/* on last use, switch off GPIO module */
286*4882a593Smuzhiyun 	if (!priv->usage_count)
287*4882a593Smuzhiyun 		gpio_twl4030_write(REG_GPIO_CTRL, 0x0);
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun out:
290*4882a593Smuzhiyun 	mutex_unlock(&priv->mutex);
291*4882a593Smuzhiyun }
292*4882a593Smuzhiyun 
twl_direction_in(struct gpio_chip * chip,unsigned offset)293*4882a593Smuzhiyun static int twl_direction_in(struct gpio_chip *chip, unsigned offset)
294*4882a593Smuzhiyun {
295*4882a593Smuzhiyun 	struct gpio_twl4030_priv *priv = gpiochip_get_data(chip);
296*4882a593Smuzhiyun 	int ret;
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun 	mutex_lock(&priv->mutex);
299*4882a593Smuzhiyun 	if (offset < TWL4030_GPIO_MAX)
300*4882a593Smuzhiyun 		ret = twl4030_set_gpio_direction(offset, 1);
301*4882a593Smuzhiyun 	else
302*4882a593Smuzhiyun 		ret = -EINVAL;	/* LED outputs can't be set as input */
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun 	if (!ret)
305*4882a593Smuzhiyun 		priv->direction &= ~BIT(offset);
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun 	mutex_unlock(&priv->mutex);
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun 	return ret;
310*4882a593Smuzhiyun }
311*4882a593Smuzhiyun 
twl_get(struct gpio_chip * chip,unsigned offset)312*4882a593Smuzhiyun static int twl_get(struct gpio_chip *chip, unsigned offset)
313*4882a593Smuzhiyun {
314*4882a593Smuzhiyun 	struct gpio_twl4030_priv *priv = gpiochip_get_data(chip);
315*4882a593Smuzhiyun 	int ret;
316*4882a593Smuzhiyun 	int status = 0;
317*4882a593Smuzhiyun 
318*4882a593Smuzhiyun 	mutex_lock(&priv->mutex);
319*4882a593Smuzhiyun 	if (!(priv->usage_count & BIT(offset))) {
320*4882a593Smuzhiyun 		ret = -EPERM;
321*4882a593Smuzhiyun 		goto out;
322*4882a593Smuzhiyun 	}
323*4882a593Smuzhiyun 
324*4882a593Smuzhiyun 	if (priv->direction & BIT(offset))
325*4882a593Smuzhiyun 		status = priv->out_state & BIT(offset);
326*4882a593Smuzhiyun 	else
327*4882a593Smuzhiyun 		status = twl4030_get_gpio_datain(offset);
328*4882a593Smuzhiyun 
329*4882a593Smuzhiyun 	ret = (status < 0) ? status : !!status;
330*4882a593Smuzhiyun out:
331*4882a593Smuzhiyun 	mutex_unlock(&priv->mutex);
332*4882a593Smuzhiyun 	return ret;
333*4882a593Smuzhiyun }
334*4882a593Smuzhiyun 
twl_set(struct gpio_chip * chip,unsigned offset,int value)335*4882a593Smuzhiyun static void twl_set(struct gpio_chip *chip, unsigned offset, int value)
336*4882a593Smuzhiyun {
337*4882a593Smuzhiyun 	struct gpio_twl4030_priv *priv = gpiochip_get_data(chip);
338*4882a593Smuzhiyun 
339*4882a593Smuzhiyun 	mutex_lock(&priv->mutex);
340*4882a593Smuzhiyun 	if (offset < TWL4030_GPIO_MAX)
341*4882a593Smuzhiyun 		twl4030_set_gpio_dataout(offset, value);
342*4882a593Smuzhiyun 	else
343*4882a593Smuzhiyun 		twl4030_led_set_value(offset - TWL4030_GPIO_MAX, value);
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun 	if (value)
346*4882a593Smuzhiyun 		priv->out_state |= BIT(offset);
347*4882a593Smuzhiyun 	else
348*4882a593Smuzhiyun 		priv->out_state &= ~BIT(offset);
349*4882a593Smuzhiyun 
350*4882a593Smuzhiyun 	mutex_unlock(&priv->mutex);
351*4882a593Smuzhiyun }
352*4882a593Smuzhiyun 
twl_direction_out(struct gpio_chip * chip,unsigned offset,int value)353*4882a593Smuzhiyun static int twl_direction_out(struct gpio_chip *chip, unsigned offset, int value)
354*4882a593Smuzhiyun {
355*4882a593Smuzhiyun 	struct gpio_twl4030_priv *priv = gpiochip_get_data(chip);
356*4882a593Smuzhiyun 	int ret = 0;
357*4882a593Smuzhiyun 
358*4882a593Smuzhiyun 	mutex_lock(&priv->mutex);
359*4882a593Smuzhiyun 	if (offset < TWL4030_GPIO_MAX) {
360*4882a593Smuzhiyun 		ret = twl4030_set_gpio_direction(offset, 0);
361*4882a593Smuzhiyun 		if (ret) {
362*4882a593Smuzhiyun 			mutex_unlock(&priv->mutex);
363*4882a593Smuzhiyun 			return ret;
364*4882a593Smuzhiyun 		}
365*4882a593Smuzhiyun 	}
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun 	/*
368*4882a593Smuzhiyun 	 *  LED gpios i.e. offset >= TWL4030_GPIO_MAX are always output
369*4882a593Smuzhiyun 	 */
370*4882a593Smuzhiyun 
371*4882a593Smuzhiyun 	priv->direction |= BIT(offset);
372*4882a593Smuzhiyun 	mutex_unlock(&priv->mutex);
373*4882a593Smuzhiyun 
374*4882a593Smuzhiyun 	twl_set(chip, offset, value);
375*4882a593Smuzhiyun 
376*4882a593Smuzhiyun 	return ret;
377*4882a593Smuzhiyun }
378*4882a593Smuzhiyun 
twl_get_direction(struct gpio_chip * chip,unsigned offset)379*4882a593Smuzhiyun static int twl_get_direction(struct gpio_chip *chip, unsigned offset)
380*4882a593Smuzhiyun {
381*4882a593Smuzhiyun 	struct gpio_twl4030_priv *priv = gpiochip_get_data(chip);
382*4882a593Smuzhiyun 	/*
383*4882a593Smuzhiyun 	 * Default GPIO_LINE_DIRECTION_OUT
384*4882a593Smuzhiyun 	 * LED GPIOs >= TWL4030_GPIO_MAX are always output
385*4882a593Smuzhiyun 	 */
386*4882a593Smuzhiyun 	int ret = GPIO_LINE_DIRECTION_OUT;
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun 	mutex_lock(&priv->mutex);
389*4882a593Smuzhiyun 	if (offset < TWL4030_GPIO_MAX) {
390*4882a593Smuzhiyun 		ret = twl4030_get_gpio_direction(offset);
391*4882a593Smuzhiyun 		if (ret) {
392*4882a593Smuzhiyun 			mutex_unlock(&priv->mutex);
393*4882a593Smuzhiyun 			return ret;
394*4882a593Smuzhiyun 		}
395*4882a593Smuzhiyun 	}
396*4882a593Smuzhiyun 	mutex_unlock(&priv->mutex);
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun 	return ret;
399*4882a593Smuzhiyun }
400*4882a593Smuzhiyun 
twl_to_irq(struct gpio_chip * chip,unsigned offset)401*4882a593Smuzhiyun static int twl_to_irq(struct gpio_chip *chip, unsigned offset)
402*4882a593Smuzhiyun {
403*4882a593Smuzhiyun 	struct gpio_twl4030_priv *priv = gpiochip_get_data(chip);
404*4882a593Smuzhiyun 
405*4882a593Smuzhiyun 	return (priv->irq_base && (offset < TWL4030_GPIO_MAX))
406*4882a593Smuzhiyun 		? (priv->irq_base + offset)
407*4882a593Smuzhiyun 		: -EINVAL;
408*4882a593Smuzhiyun }
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun static const struct gpio_chip template_chip = {
411*4882a593Smuzhiyun 	.label			= "twl4030",
412*4882a593Smuzhiyun 	.owner			= THIS_MODULE,
413*4882a593Smuzhiyun 	.request		= twl_request,
414*4882a593Smuzhiyun 	.free			= twl_free,
415*4882a593Smuzhiyun 	.direction_input	= twl_direction_in,
416*4882a593Smuzhiyun 	.direction_output	= twl_direction_out,
417*4882a593Smuzhiyun 	.get_direction		= twl_get_direction,
418*4882a593Smuzhiyun 	.get			= twl_get,
419*4882a593Smuzhiyun 	.set			= twl_set,
420*4882a593Smuzhiyun 	.to_irq			= twl_to_irq,
421*4882a593Smuzhiyun 	.can_sleep		= true,
422*4882a593Smuzhiyun };
423*4882a593Smuzhiyun 
424*4882a593Smuzhiyun /*----------------------------------------------------------------------*/
425*4882a593Smuzhiyun 
gpio_twl4030_pulls(u32 ups,u32 downs)426*4882a593Smuzhiyun static int gpio_twl4030_pulls(u32 ups, u32 downs)
427*4882a593Smuzhiyun {
428*4882a593Smuzhiyun 	u8		message[5];
429*4882a593Smuzhiyun 	unsigned	i, gpio_bit;
430*4882a593Smuzhiyun 
431*4882a593Smuzhiyun 	/* For most pins, a pulldown was enabled by default.
432*4882a593Smuzhiyun 	 * We should have data that's specific to this board.
433*4882a593Smuzhiyun 	 */
434*4882a593Smuzhiyun 	for (gpio_bit = 1, i = 0; i < 5; i++) {
435*4882a593Smuzhiyun 		u8		bit_mask;
436*4882a593Smuzhiyun 		unsigned	j;
437*4882a593Smuzhiyun 
438*4882a593Smuzhiyun 		for (bit_mask = 0, j = 0; j < 8; j += 2, gpio_bit <<= 1) {
439*4882a593Smuzhiyun 			if (ups & gpio_bit)
440*4882a593Smuzhiyun 				bit_mask |= 1 << (j + 1);
441*4882a593Smuzhiyun 			else if (downs & gpio_bit)
442*4882a593Smuzhiyun 				bit_mask |= 1 << (j + 0);
443*4882a593Smuzhiyun 		}
444*4882a593Smuzhiyun 		message[i] = bit_mask;
445*4882a593Smuzhiyun 	}
446*4882a593Smuzhiyun 
447*4882a593Smuzhiyun 	return twl_i2c_write(TWL4030_MODULE_GPIO, message,
448*4882a593Smuzhiyun 				REG_GPIOPUPDCTR1, 5);
449*4882a593Smuzhiyun }
450*4882a593Smuzhiyun 
gpio_twl4030_debounce(u32 debounce,u8 mmc_cd)451*4882a593Smuzhiyun static int gpio_twl4030_debounce(u32 debounce, u8 mmc_cd)
452*4882a593Smuzhiyun {
453*4882a593Smuzhiyun 	u8		message[3];
454*4882a593Smuzhiyun 
455*4882a593Smuzhiyun 	/* 30 msec of debouncing is always used for MMC card detect,
456*4882a593Smuzhiyun 	 * and is optional for everything else.
457*4882a593Smuzhiyun 	 */
458*4882a593Smuzhiyun 	message[0] = (debounce & 0xff) | (mmc_cd & 0x03);
459*4882a593Smuzhiyun 	debounce >>= 8;
460*4882a593Smuzhiyun 	message[1] = (debounce & 0xff);
461*4882a593Smuzhiyun 	debounce >>= 8;
462*4882a593Smuzhiyun 	message[2] = (debounce & 0x03);
463*4882a593Smuzhiyun 
464*4882a593Smuzhiyun 	return twl_i2c_write(TWL4030_MODULE_GPIO, message,
465*4882a593Smuzhiyun 				REG_GPIO_DEBEN1, 3);
466*4882a593Smuzhiyun }
467*4882a593Smuzhiyun 
468*4882a593Smuzhiyun static int gpio_twl4030_remove(struct platform_device *pdev);
469*4882a593Smuzhiyun 
of_gpio_twl4030(struct device * dev,struct twl4030_gpio_platform_data * pdata)470*4882a593Smuzhiyun static struct twl4030_gpio_platform_data *of_gpio_twl4030(struct device *dev,
471*4882a593Smuzhiyun 				struct twl4030_gpio_platform_data *pdata)
472*4882a593Smuzhiyun {
473*4882a593Smuzhiyun 	struct twl4030_gpio_platform_data *omap_twl_info;
474*4882a593Smuzhiyun 
475*4882a593Smuzhiyun 	omap_twl_info = devm_kzalloc(dev, sizeof(*omap_twl_info), GFP_KERNEL);
476*4882a593Smuzhiyun 	if (!omap_twl_info)
477*4882a593Smuzhiyun 		return NULL;
478*4882a593Smuzhiyun 
479*4882a593Smuzhiyun 	if (pdata)
480*4882a593Smuzhiyun 		*omap_twl_info = *pdata;
481*4882a593Smuzhiyun 
482*4882a593Smuzhiyun 	omap_twl_info->use_leds = of_property_read_bool(dev->of_node,
483*4882a593Smuzhiyun 			"ti,use-leds");
484*4882a593Smuzhiyun 
485*4882a593Smuzhiyun 	of_property_read_u32(dev->of_node, "ti,debounce",
486*4882a593Smuzhiyun 			     &omap_twl_info->debounce);
487*4882a593Smuzhiyun 	of_property_read_u32(dev->of_node, "ti,mmc-cd",
488*4882a593Smuzhiyun 			     (u32 *)&omap_twl_info->mmc_cd);
489*4882a593Smuzhiyun 	of_property_read_u32(dev->of_node, "ti,pullups",
490*4882a593Smuzhiyun 			     &omap_twl_info->pullups);
491*4882a593Smuzhiyun 	of_property_read_u32(dev->of_node, "ti,pulldowns",
492*4882a593Smuzhiyun 			     &omap_twl_info->pulldowns);
493*4882a593Smuzhiyun 
494*4882a593Smuzhiyun 	return omap_twl_info;
495*4882a593Smuzhiyun }
496*4882a593Smuzhiyun 
gpio_twl4030_probe(struct platform_device * pdev)497*4882a593Smuzhiyun static int gpio_twl4030_probe(struct platform_device *pdev)
498*4882a593Smuzhiyun {
499*4882a593Smuzhiyun 	struct twl4030_gpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
500*4882a593Smuzhiyun 	struct device_node *node = pdev->dev.of_node;
501*4882a593Smuzhiyun 	struct gpio_twl4030_priv *priv;
502*4882a593Smuzhiyun 	int ret, irq_base;
503*4882a593Smuzhiyun 
504*4882a593Smuzhiyun 	priv = devm_kzalloc(&pdev->dev, sizeof(struct gpio_twl4030_priv),
505*4882a593Smuzhiyun 			    GFP_KERNEL);
506*4882a593Smuzhiyun 	if (!priv)
507*4882a593Smuzhiyun 		return -ENOMEM;
508*4882a593Smuzhiyun 
509*4882a593Smuzhiyun 	/* maybe setup IRQs */
510*4882a593Smuzhiyun 	if (is_module()) {
511*4882a593Smuzhiyun 		dev_err(&pdev->dev, "can't dispatch IRQs from modules\n");
512*4882a593Smuzhiyun 		goto no_irqs;
513*4882a593Smuzhiyun 	}
514*4882a593Smuzhiyun 
515*4882a593Smuzhiyun 	irq_base = devm_irq_alloc_descs(&pdev->dev, -1,
516*4882a593Smuzhiyun 					0, TWL4030_GPIO_MAX, 0);
517*4882a593Smuzhiyun 	if (irq_base < 0) {
518*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Failed to alloc irq_descs\n");
519*4882a593Smuzhiyun 		return irq_base;
520*4882a593Smuzhiyun 	}
521*4882a593Smuzhiyun 
522*4882a593Smuzhiyun 	irq_domain_add_legacy(node, TWL4030_GPIO_MAX, irq_base, 0,
523*4882a593Smuzhiyun 			      &irq_domain_simple_ops, NULL);
524*4882a593Smuzhiyun 
525*4882a593Smuzhiyun 	ret = twl4030_sih_setup(&pdev->dev, TWL4030_MODULE_GPIO, irq_base);
526*4882a593Smuzhiyun 	if (ret < 0)
527*4882a593Smuzhiyun 		return ret;
528*4882a593Smuzhiyun 
529*4882a593Smuzhiyun 	priv->irq_base = irq_base;
530*4882a593Smuzhiyun 
531*4882a593Smuzhiyun no_irqs:
532*4882a593Smuzhiyun 	priv->gpio_chip = template_chip;
533*4882a593Smuzhiyun 	priv->gpio_chip.base = -1;
534*4882a593Smuzhiyun 	priv->gpio_chip.ngpio = TWL4030_GPIO_MAX;
535*4882a593Smuzhiyun 	priv->gpio_chip.parent = &pdev->dev;
536*4882a593Smuzhiyun 
537*4882a593Smuzhiyun 	mutex_init(&priv->mutex);
538*4882a593Smuzhiyun 
539*4882a593Smuzhiyun 	if (node)
540*4882a593Smuzhiyun 		pdata = of_gpio_twl4030(&pdev->dev, pdata);
541*4882a593Smuzhiyun 
542*4882a593Smuzhiyun 	if (pdata == NULL) {
543*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Platform data is missing\n");
544*4882a593Smuzhiyun 		return -ENXIO;
545*4882a593Smuzhiyun 	}
546*4882a593Smuzhiyun 
547*4882a593Smuzhiyun 	/*
548*4882a593Smuzhiyun 	 * NOTE:  boards may waste power if they don't set pullups
549*4882a593Smuzhiyun 	 * and pulldowns correctly ... default for non-ULPI pins is
550*4882a593Smuzhiyun 	 * pulldown, and some other pins may have external pullups
551*4882a593Smuzhiyun 	 * or pulldowns.  Careful!
552*4882a593Smuzhiyun 	 */
553*4882a593Smuzhiyun 	ret = gpio_twl4030_pulls(pdata->pullups, pdata->pulldowns);
554*4882a593Smuzhiyun 	if (ret)
555*4882a593Smuzhiyun 		dev_dbg(&pdev->dev, "pullups %.05x %.05x --> %d\n",
556*4882a593Smuzhiyun 			pdata->pullups, pdata->pulldowns, ret);
557*4882a593Smuzhiyun 
558*4882a593Smuzhiyun 	ret = gpio_twl4030_debounce(pdata->debounce, pdata->mmc_cd);
559*4882a593Smuzhiyun 	if (ret)
560*4882a593Smuzhiyun 		dev_dbg(&pdev->dev, "debounce %.03x %.01x --> %d\n",
561*4882a593Smuzhiyun 			pdata->debounce, pdata->mmc_cd, ret);
562*4882a593Smuzhiyun 
563*4882a593Smuzhiyun 	/*
564*4882a593Smuzhiyun 	 * NOTE: we assume VIBRA_CTL.VIBRA_EN, in MODULE_AUDIO_VOICE,
565*4882a593Smuzhiyun 	 * is (still) clear if use_leds is set.
566*4882a593Smuzhiyun 	 */
567*4882a593Smuzhiyun 	if (pdata->use_leds)
568*4882a593Smuzhiyun 		priv->gpio_chip.ngpio += 2;
569*4882a593Smuzhiyun 
570*4882a593Smuzhiyun 	ret = gpiochip_add_data(&priv->gpio_chip, priv);
571*4882a593Smuzhiyun 	if (ret < 0) {
572*4882a593Smuzhiyun 		dev_err(&pdev->dev, "could not register gpiochip, %d\n", ret);
573*4882a593Smuzhiyun 		priv->gpio_chip.ngpio = 0;
574*4882a593Smuzhiyun 		gpio_twl4030_remove(pdev);
575*4882a593Smuzhiyun 		goto out;
576*4882a593Smuzhiyun 	}
577*4882a593Smuzhiyun 
578*4882a593Smuzhiyun 	platform_set_drvdata(pdev, priv);
579*4882a593Smuzhiyun 
580*4882a593Smuzhiyun 	if (pdata->setup) {
581*4882a593Smuzhiyun 		int status;
582*4882a593Smuzhiyun 
583*4882a593Smuzhiyun 		status = pdata->setup(&pdev->dev, priv->gpio_chip.base,
584*4882a593Smuzhiyun 				      TWL4030_GPIO_MAX);
585*4882a593Smuzhiyun 		if (status)
586*4882a593Smuzhiyun 			dev_dbg(&pdev->dev, "setup --> %d\n", status);
587*4882a593Smuzhiyun 	}
588*4882a593Smuzhiyun 
589*4882a593Smuzhiyun out:
590*4882a593Smuzhiyun 	return ret;
591*4882a593Smuzhiyun }
592*4882a593Smuzhiyun 
593*4882a593Smuzhiyun /* Cannot use as gpio_twl4030_probe() calls us */
gpio_twl4030_remove(struct platform_device * pdev)594*4882a593Smuzhiyun static int gpio_twl4030_remove(struct platform_device *pdev)
595*4882a593Smuzhiyun {
596*4882a593Smuzhiyun 	struct twl4030_gpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
597*4882a593Smuzhiyun 	struct gpio_twl4030_priv *priv = platform_get_drvdata(pdev);
598*4882a593Smuzhiyun 	int status;
599*4882a593Smuzhiyun 
600*4882a593Smuzhiyun 	if (pdata && pdata->teardown) {
601*4882a593Smuzhiyun 		status = pdata->teardown(&pdev->dev, priv->gpio_chip.base,
602*4882a593Smuzhiyun 					 TWL4030_GPIO_MAX);
603*4882a593Smuzhiyun 		if (status) {
604*4882a593Smuzhiyun 			dev_dbg(&pdev->dev, "teardown --> %d\n", status);
605*4882a593Smuzhiyun 			return status;
606*4882a593Smuzhiyun 		}
607*4882a593Smuzhiyun 	}
608*4882a593Smuzhiyun 
609*4882a593Smuzhiyun 	gpiochip_remove(&priv->gpio_chip);
610*4882a593Smuzhiyun 
611*4882a593Smuzhiyun 	if (is_module())
612*4882a593Smuzhiyun 		return 0;
613*4882a593Smuzhiyun 
614*4882a593Smuzhiyun 	/* REVISIT no support yet for deregistering all the IRQs */
615*4882a593Smuzhiyun 	WARN_ON(1);
616*4882a593Smuzhiyun 	return -EIO;
617*4882a593Smuzhiyun }
618*4882a593Smuzhiyun 
619*4882a593Smuzhiyun static const struct of_device_id twl_gpio_match[] = {
620*4882a593Smuzhiyun 	{ .compatible = "ti,twl4030-gpio", },
621*4882a593Smuzhiyun 	{ },
622*4882a593Smuzhiyun };
623*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, twl_gpio_match);
624*4882a593Smuzhiyun 
625*4882a593Smuzhiyun /* Note:  this hardware lives inside an I2C-based multi-function device. */
626*4882a593Smuzhiyun MODULE_ALIAS("platform:twl4030_gpio");
627*4882a593Smuzhiyun 
628*4882a593Smuzhiyun static struct platform_driver gpio_twl4030_driver = {
629*4882a593Smuzhiyun 	.driver = {
630*4882a593Smuzhiyun 		.name	= "twl4030_gpio",
631*4882a593Smuzhiyun 		.of_match_table = twl_gpio_match,
632*4882a593Smuzhiyun 	},
633*4882a593Smuzhiyun 	.probe		= gpio_twl4030_probe,
634*4882a593Smuzhiyun 	.remove		= gpio_twl4030_remove,
635*4882a593Smuzhiyun };
636*4882a593Smuzhiyun 
gpio_twl4030_init(void)637*4882a593Smuzhiyun static int __init gpio_twl4030_init(void)
638*4882a593Smuzhiyun {
639*4882a593Smuzhiyun 	return platform_driver_register(&gpio_twl4030_driver);
640*4882a593Smuzhiyun }
641*4882a593Smuzhiyun subsys_initcall(gpio_twl4030_init);
642*4882a593Smuzhiyun 
gpio_twl4030_exit(void)643*4882a593Smuzhiyun static void __exit gpio_twl4030_exit(void)
644*4882a593Smuzhiyun {
645*4882a593Smuzhiyun 	platform_driver_unregister(&gpio_twl4030_driver);
646*4882a593Smuzhiyun }
647*4882a593Smuzhiyun module_exit(gpio_twl4030_exit);
648*4882a593Smuzhiyun 
649*4882a593Smuzhiyun MODULE_AUTHOR("Texas Instruments, Inc.");
650*4882a593Smuzhiyun MODULE_DESCRIPTION("GPIO interface for TWL4030");
651*4882a593Smuzhiyun MODULE_LICENSE("GPL");
652