1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /* Abilis Systems MODULE DESCRIPTION
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) Abilis Systems 2013
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Authors: Sascha Leuenberger <sascha.leuenberger@abilis.com>
7*4882a593Smuzhiyun * Christian Ruppert <christian.ruppert@abilis.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/kernel.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/platform_device.h>
13*4882a593Smuzhiyun #include <linux/gpio/driver.h>
14*4882a593Smuzhiyun #include <linux/slab.h>
15*4882a593Smuzhiyun #include <linux/irq.h>
16*4882a593Smuzhiyun #include <linux/irqdomain.h>
17*4882a593Smuzhiyun #include <linux/interrupt.h>
18*4882a593Smuzhiyun #include <linux/io.h>
19*4882a593Smuzhiyun #include <linux/of.h>
20*4882a593Smuzhiyun #include <linux/of_platform.h>
21*4882a593Smuzhiyun #include <linux/spinlock.h>
22*4882a593Smuzhiyun #include <linux/bitops.h>
23*4882a593Smuzhiyun #include <linux/pinctrl/consumer.h>
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define TB10X_GPIO_DIR_IN (0x00000000)
26*4882a593Smuzhiyun #define TB10X_GPIO_DIR_OUT (0x00000001)
27*4882a593Smuzhiyun #define OFFSET_TO_REG_DDR (0x00)
28*4882a593Smuzhiyun #define OFFSET_TO_REG_DATA (0x04)
29*4882a593Smuzhiyun #define OFFSET_TO_REG_INT_EN (0x08)
30*4882a593Smuzhiyun #define OFFSET_TO_REG_CHANGE (0x0C)
31*4882a593Smuzhiyun #define OFFSET_TO_REG_WRMASK (0x10)
32*4882a593Smuzhiyun #define OFFSET_TO_REG_INT_TYPE (0x14)
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /**
36*4882a593Smuzhiyun * @base: register base address
37*4882a593Smuzhiyun * @domain: IRQ domain of GPIO generated interrupts managed by this controller
38*4882a593Smuzhiyun * @irq: Interrupt line of parent interrupt controller
39*4882a593Smuzhiyun * @gc: gpio_chip structure associated to this GPIO controller
40*4882a593Smuzhiyun */
41*4882a593Smuzhiyun struct tb10x_gpio {
42*4882a593Smuzhiyun void __iomem *base;
43*4882a593Smuzhiyun struct irq_domain *domain;
44*4882a593Smuzhiyun int irq;
45*4882a593Smuzhiyun struct gpio_chip gc;
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun
tb10x_reg_read(struct tb10x_gpio * gpio,unsigned int offs)48*4882a593Smuzhiyun static inline u32 tb10x_reg_read(struct tb10x_gpio *gpio, unsigned int offs)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun return ioread32(gpio->base + offs);
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
tb10x_reg_write(struct tb10x_gpio * gpio,unsigned int offs,u32 val)53*4882a593Smuzhiyun static inline void tb10x_reg_write(struct tb10x_gpio *gpio, unsigned int offs,
54*4882a593Smuzhiyun u32 val)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun iowrite32(val, gpio->base + offs);
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
tb10x_set_bits(struct tb10x_gpio * gpio,unsigned int offs,u32 mask,u32 val)59*4882a593Smuzhiyun static inline void tb10x_set_bits(struct tb10x_gpio *gpio, unsigned int offs,
60*4882a593Smuzhiyun u32 mask, u32 val)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun u32 r;
63*4882a593Smuzhiyun unsigned long flags;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun spin_lock_irqsave(&gpio->gc.bgpio_lock, flags);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun r = tb10x_reg_read(gpio, offs);
68*4882a593Smuzhiyun r = (r & ~mask) | (val & mask);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun tb10x_reg_write(gpio, offs, r);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun spin_unlock_irqrestore(&gpio->gc.bgpio_lock, flags);
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
tb10x_gpio_to_irq(struct gpio_chip * chip,unsigned offset)75*4882a593Smuzhiyun static int tb10x_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun struct tb10x_gpio *tb10x_gpio = gpiochip_get_data(chip);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun return irq_create_mapping(tb10x_gpio->domain, offset);
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
tb10x_gpio_irq_set_type(struct irq_data * data,unsigned int type)82*4882a593Smuzhiyun static int tb10x_gpio_irq_set_type(struct irq_data *data, unsigned int type)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun if ((type & IRQF_TRIGGER_MASK) != IRQ_TYPE_EDGE_BOTH) {
85*4882a593Smuzhiyun pr_err("Only (both) edge triggered interrupts supported.\n");
86*4882a593Smuzhiyun return -EINVAL;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun irqd_set_trigger_type(data, type);
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun return IRQ_SET_MASK_OK;
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
tb10x_gpio_irq_cascade(int irq,void * data)94*4882a593Smuzhiyun static irqreturn_t tb10x_gpio_irq_cascade(int irq, void *data)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun struct tb10x_gpio *tb10x_gpio = data;
97*4882a593Smuzhiyun u32 r = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_CHANGE);
98*4882a593Smuzhiyun u32 m = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_INT_EN);
99*4882a593Smuzhiyun const unsigned long bits = r & m;
100*4882a593Smuzhiyun int i;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun for_each_set_bit(i, &bits, 32)
103*4882a593Smuzhiyun generic_handle_irq(irq_find_mapping(tb10x_gpio->domain, i));
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun return IRQ_HANDLED;
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
tb10x_gpio_probe(struct platform_device * pdev)108*4882a593Smuzhiyun static int tb10x_gpio_probe(struct platform_device *pdev)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun struct tb10x_gpio *tb10x_gpio;
111*4882a593Smuzhiyun struct device *dev = &pdev->dev;
112*4882a593Smuzhiyun struct device_node *np = dev->of_node;
113*4882a593Smuzhiyun int ret = -EBUSY;
114*4882a593Smuzhiyun u32 ngpio;
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun if (!np)
117*4882a593Smuzhiyun return -EINVAL;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun if (of_property_read_u32(np, "abilis,ngpio", &ngpio))
120*4882a593Smuzhiyun return -EINVAL;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun tb10x_gpio = devm_kzalloc(dev, sizeof(*tb10x_gpio), GFP_KERNEL);
123*4882a593Smuzhiyun if (tb10x_gpio == NULL)
124*4882a593Smuzhiyun return -ENOMEM;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun tb10x_gpio->base = devm_platform_ioremap_resource(pdev, 0);
127*4882a593Smuzhiyun if (IS_ERR(tb10x_gpio->base))
128*4882a593Smuzhiyun return PTR_ERR(tb10x_gpio->base);
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun tb10x_gpio->gc.label =
131*4882a593Smuzhiyun devm_kasprintf(dev, GFP_KERNEL, "%pOF", pdev->dev.of_node);
132*4882a593Smuzhiyun if (!tb10x_gpio->gc.label)
133*4882a593Smuzhiyun return -ENOMEM;
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun /*
136*4882a593Smuzhiyun * Initialize generic GPIO with one single register for reading and setting
137*4882a593Smuzhiyun * the lines, no special set or clear registers and a data direction register
138*4882a593Smuzhiyun * wher 1 means "output".
139*4882a593Smuzhiyun */
140*4882a593Smuzhiyun ret = bgpio_init(&tb10x_gpio->gc, dev, 4,
141*4882a593Smuzhiyun tb10x_gpio->base + OFFSET_TO_REG_DATA,
142*4882a593Smuzhiyun NULL,
143*4882a593Smuzhiyun NULL,
144*4882a593Smuzhiyun tb10x_gpio->base + OFFSET_TO_REG_DDR,
145*4882a593Smuzhiyun NULL,
146*4882a593Smuzhiyun 0);
147*4882a593Smuzhiyun if (ret) {
148*4882a593Smuzhiyun dev_err(dev, "unable to init generic GPIO\n");
149*4882a593Smuzhiyun return ret;
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun tb10x_gpio->gc.base = -1;
152*4882a593Smuzhiyun tb10x_gpio->gc.parent = dev;
153*4882a593Smuzhiyun tb10x_gpio->gc.owner = THIS_MODULE;
154*4882a593Smuzhiyun /*
155*4882a593Smuzhiyun * ngpio is set by bgpio_init() but we override it, this .request()
156*4882a593Smuzhiyun * callback also overrides the one set up by generic GPIO.
157*4882a593Smuzhiyun */
158*4882a593Smuzhiyun tb10x_gpio->gc.ngpio = ngpio;
159*4882a593Smuzhiyun tb10x_gpio->gc.request = gpiochip_generic_request;
160*4882a593Smuzhiyun tb10x_gpio->gc.free = gpiochip_generic_free;
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun ret = devm_gpiochip_add_data(dev, &tb10x_gpio->gc, tb10x_gpio);
163*4882a593Smuzhiyun if (ret < 0) {
164*4882a593Smuzhiyun dev_err(dev, "Could not add gpiochip.\n");
165*4882a593Smuzhiyun return ret;
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun platform_set_drvdata(pdev, tb10x_gpio);
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun if (of_find_property(np, "interrupt-controller", NULL)) {
171*4882a593Smuzhiyun struct irq_chip_generic *gc;
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun ret = platform_get_irq(pdev, 0);
174*4882a593Smuzhiyun if (ret < 0)
175*4882a593Smuzhiyun return ret;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun tb10x_gpio->gc.to_irq = tb10x_gpio_to_irq;
178*4882a593Smuzhiyun tb10x_gpio->irq = ret;
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun ret = devm_request_irq(dev, ret, tb10x_gpio_irq_cascade,
181*4882a593Smuzhiyun IRQF_TRIGGER_NONE | IRQF_SHARED,
182*4882a593Smuzhiyun dev_name(dev), tb10x_gpio);
183*4882a593Smuzhiyun if (ret != 0)
184*4882a593Smuzhiyun return ret;
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun tb10x_gpio->domain = irq_domain_add_linear(np,
187*4882a593Smuzhiyun tb10x_gpio->gc.ngpio,
188*4882a593Smuzhiyun &irq_generic_chip_ops, NULL);
189*4882a593Smuzhiyun if (!tb10x_gpio->domain) {
190*4882a593Smuzhiyun return -ENOMEM;
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun ret = irq_alloc_domain_generic_chips(tb10x_gpio->domain,
194*4882a593Smuzhiyun tb10x_gpio->gc.ngpio, 1, tb10x_gpio->gc.label,
195*4882a593Smuzhiyun handle_edge_irq, IRQ_NOREQUEST, IRQ_NOPROBE,
196*4882a593Smuzhiyun IRQ_GC_INIT_MASK_CACHE);
197*4882a593Smuzhiyun if (ret)
198*4882a593Smuzhiyun return ret;
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun gc = tb10x_gpio->domain->gc->gc[0];
201*4882a593Smuzhiyun gc->reg_base = tb10x_gpio->base;
202*4882a593Smuzhiyun gc->chip_types[0].type = IRQ_TYPE_EDGE_BOTH;
203*4882a593Smuzhiyun gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
204*4882a593Smuzhiyun gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
205*4882a593Smuzhiyun gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
206*4882a593Smuzhiyun gc->chip_types[0].chip.irq_set_type = tb10x_gpio_irq_set_type;
207*4882a593Smuzhiyun gc->chip_types[0].regs.ack = OFFSET_TO_REG_CHANGE;
208*4882a593Smuzhiyun gc->chip_types[0].regs.mask = OFFSET_TO_REG_INT_EN;
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun return 0;
212*4882a593Smuzhiyun }
213*4882a593Smuzhiyun
tb10x_gpio_remove(struct platform_device * pdev)214*4882a593Smuzhiyun static int tb10x_gpio_remove(struct platform_device *pdev)
215*4882a593Smuzhiyun {
216*4882a593Smuzhiyun struct tb10x_gpio *tb10x_gpio = platform_get_drvdata(pdev);
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun if (tb10x_gpio->gc.to_irq) {
219*4882a593Smuzhiyun irq_remove_generic_chip(tb10x_gpio->domain->gc->gc[0],
220*4882a593Smuzhiyun BIT(tb10x_gpio->gc.ngpio) - 1, 0, 0);
221*4882a593Smuzhiyun kfree(tb10x_gpio->domain->gc);
222*4882a593Smuzhiyun irq_domain_remove(tb10x_gpio->domain);
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun return 0;
226*4882a593Smuzhiyun }
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun static const struct of_device_id tb10x_gpio_dt_ids[] = {
229*4882a593Smuzhiyun { .compatible = "abilis,tb10x-gpio" },
230*4882a593Smuzhiyun { }
231*4882a593Smuzhiyun };
232*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, tb10x_gpio_dt_ids);
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun static struct platform_driver tb10x_gpio_driver = {
235*4882a593Smuzhiyun .probe = tb10x_gpio_probe,
236*4882a593Smuzhiyun .remove = tb10x_gpio_remove,
237*4882a593Smuzhiyun .driver = {
238*4882a593Smuzhiyun .name = "tb10x-gpio",
239*4882a593Smuzhiyun .of_match_table = tb10x_gpio_dt_ids,
240*4882a593Smuzhiyun }
241*4882a593Smuzhiyun };
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun module_platform_driver(tb10x_gpio_driver);
244*4882a593Smuzhiyun MODULE_LICENSE("GPL");
245*4882a593Smuzhiyun MODULE_DESCRIPTION("tb10x gpio.");
246