1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * sl28cpld GPIO driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2020 Michael Walle <michael@walle.cc>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/device.h>
9*4882a593Smuzhiyun #include <linux/gpio/driver.h>
10*4882a593Smuzhiyun #include <linux/gpio/regmap.h>
11*4882a593Smuzhiyun #include <linux/interrupt.h>
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/mod_devicetable.h>
14*4882a593Smuzhiyun #include <linux/module.h>
15*4882a593Smuzhiyun #include <linux/platform_device.h>
16*4882a593Smuzhiyun #include <linux/regmap.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /* GPIO flavor */
19*4882a593Smuzhiyun #define GPIO_REG_DIR 0x00
20*4882a593Smuzhiyun #define GPIO_REG_OUT 0x01
21*4882a593Smuzhiyun #define GPIO_REG_IN 0x02
22*4882a593Smuzhiyun #define GPIO_REG_IE 0x03
23*4882a593Smuzhiyun #define GPIO_REG_IP 0x04
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* input-only flavor */
26*4882a593Smuzhiyun #define GPI_REG_IN 0x00
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* output-only flavor */
29*4882a593Smuzhiyun #define GPO_REG_OUT 0x00
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun enum sl28cpld_gpio_type {
32*4882a593Smuzhiyun SL28CPLD_GPIO = 1,
33*4882a593Smuzhiyun SL28CPLD_GPI,
34*4882a593Smuzhiyun SL28CPLD_GPO,
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun static const struct regmap_irq sl28cpld_gpio_irqs[] = {
38*4882a593Smuzhiyun REGMAP_IRQ_REG_LINE(0, 8),
39*4882a593Smuzhiyun REGMAP_IRQ_REG_LINE(1, 8),
40*4882a593Smuzhiyun REGMAP_IRQ_REG_LINE(2, 8),
41*4882a593Smuzhiyun REGMAP_IRQ_REG_LINE(3, 8),
42*4882a593Smuzhiyun REGMAP_IRQ_REG_LINE(4, 8),
43*4882a593Smuzhiyun REGMAP_IRQ_REG_LINE(5, 8),
44*4882a593Smuzhiyun REGMAP_IRQ_REG_LINE(6, 8),
45*4882a593Smuzhiyun REGMAP_IRQ_REG_LINE(7, 8),
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun
sl28cpld_gpio_irq_init(struct platform_device * pdev,unsigned int base,struct gpio_regmap_config * config)48*4882a593Smuzhiyun static int sl28cpld_gpio_irq_init(struct platform_device *pdev,
49*4882a593Smuzhiyun unsigned int base,
50*4882a593Smuzhiyun struct gpio_regmap_config *config)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun struct regmap_irq_chip_data *irq_data;
53*4882a593Smuzhiyun struct regmap_irq_chip *irq_chip;
54*4882a593Smuzhiyun struct device *dev = &pdev->dev;
55*4882a593Smuzhiyun int irq, ret;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun if (!device_property_read_bool(dev, "interrupt-controller"))
58*4882a593Smuzhiyun return 0;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun irq = platform_get_irq(pdev, 0);
61*4882a593Smuzhiyun if (irq < 0)
62*4882a593Smuzhiyun return irq;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun irq_chip = devm_kzalloc(dev, sizeof(*irq_chip), GFP_KERNEL);
65*4882a593Smuzhiyun if (!irq_chip)
66*4882a593Smuzhiyun return -ENOMEM;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun irq_chip->name = "sl28cpld-gpio-irq",
69*4882a593Smuzhiyun irq_chip->irqs = sl28cpld_gpio_irqs;
70*4882a593Smuzhiyun irq_chip->num_irqs = ARRAY_SIZE(sl28cpld_gpio_irqs);
71*4882a593Smuzhiyun irq_chip->num_regs = 1;
72*4882a593Smuzhiyun irq_chip->status_base = base + GPIO_REG_IP;
73*4882a593Smuzhiyun irq_chip->mask_base = base + GPIO_REG_IE;
74*4882a593Smuzhiyun irq_chip->mask_invert = true,
75*4882a593Smuzhiyun irq_chip->ack_base = base + GPIO_REG_IP;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun ret = devm_regmap_add_irq_chip_fwnode(dev, dev_fwnode(dev),
78*4882a593Smuzhiyun config->regmap, irq,
79*4882a593Smuzhiyun IRQF_SHARED | IRQF_ONESHOT,
80*4882a593Smuzhiyun 0, irq_chip, &irq_data);
81*4882a593Smuzhiyun if (ret)
82*4882a593Smuzhiyun return ret;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun config->irq_domain = regmap_irq_get_domain(irq_data);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun return 0;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
sl28cpld_gpio_probe(struct platform_device * pdev)89*4882a593Smuzhiyun static int sl28cpld_gpio_probe(struct platform_device *pdev)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun struct gpio_regmap_config config = {0};
92*4882a593Smuzhiyun enum sl28cpld_gpio_type type;
93*4882a593Smuzhiyun struct regmap *regmap;
94*4882a593Smuzhiyun u32 base;
95*4882a593Smuzhiyun int ret;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun if (!pdev->dev.parent)
98*4882a593Smuzhiyun return -ENODEV;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun type = (uintptr_t)device_get_match_data(&pdev->dev);
101*4882a593Smuzhiyun if (!type)
102*4882a593Smuzhiyun return -ENODEV;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun ret = device_property_read_u32(&pdev->dev, "reg", &base);
105*4882a593Smuzhiyun if (ret)
106*4882a593Smuzhiyun return -EINVAL;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun regmap = dev_get_regmap(pdev->dev.parent, NULL);
109*4882a593Smuzhiyun if (!regmap)
110*4882a593Smuzhiyun return -ENODEV;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun config.regmap = regmap;
113*4882a593Smuzhiyun config.parent = &pdev->dev;
114*4882a593Smuzhiyun config.ngpio = 8;
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun switch (type) {
117*4882a593Smuzhiyun case SL28CPLD_GPIO:
118*4882a593Smuzhiyun config.reg_dat_base = base + GPIO_REG_IN;
119*4882a593Smuzhiyun config.reg_set_base = base + GPIO_REG_OUT;
120*4882a593Smuzhiyun /* reg_dir_out_base might be zero */
121*4882a593Smuzhiyun config.reg_dir_out_base = GPIO_REGMAP_ADDR(base + GPIO_REG_DIR);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun /* This type supports interrupts */
124*4882a593Smuzhiyun ret = sl28cpld_gpio_irq_init(pdev, base, &config);
125*4882a593Smuzhiyun if (ret)
126*4882a593Smuzhiyun return ret;
127*4882a593Smuzhiyun break;
128*4882a593Smuzhiyun case SL28CPLD_GPO:
129*4882a593Smuzhiyun config.reg_set_base = base + GPO_REG_OUT;
130*4882a593Smuzhiyun break;
131*4882a593Smuzhiyun case SL28CPLD_GPI:
132*4882a593Smuzhiyun config.reg_dat_base = base + GPI_REG_IN;
133*4882a593Smuzhiyun break;
134*4882a593Smuzhiyun default:
135*4882a593Smuzhiyun dev_err(&pdev->dev, "unknown type %d\n", type);
136*4882a593Smuzhiyun return -ENODEV;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(&pdev->dev, &config));
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun static const struct of_device_id sl28cpld_gpio_of_match[] = {
143*4882a593Smuzhiyun { .compatible = "kontron,sl28cpld-gpio", .data = (void *)SL28CPLD_GPIO },
144*4882a593Smuzhiyun { .compatible = "kontron,sl28cpld-gpi", .data = (void *)SL28CPLD_GPI },
145*4882a593Smuzhiyun { .compatible = "kontron,sl28cpld-gpo", .data = (void *)SL28CPLD_GPO },
146*4882a593Smuzhiyun {}
147*4882a593Smuzhiyun };
148*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, sl28cpld_gpio_of_match);
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun static struct platform_driver sl28cpld_gpio_driver = {
151*4882a593Smuzhiyun .probe = sl28cpld_gpio_probe,
152*4882a593Smuzhiyun .driver = {
153*4882a593Smuzhiyun .name = "sl28cpld-gpio",
154*4882a593Smuzhiyun .of_match_table = sl28cpld_gpio_of_match,
155*4882a593Smuzhiyun },
156*4882a593Smuzhiyun };
157*4882a593Smuzhiyun module_platform_driver(sl28cpld_gpio_driver);
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun MODULE_DESCRIPTION("sl28cpld GPIO Driver");
160*4882a593Smuzhiyun MODULE_AUTHOR("Michael Walle <michael@walle.cc>");
161*4882a593Smuzhiyun MODULE_LICENSE("GPL");
162