1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * GPIO driver for the SMSC SCH311x Super-I/O chips
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2013 Bruno Randolf <br1@einfach.org>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SuperIO functions and chip detection:
8*4882a593Smuzhiyun * (c) Copyright 2008 Wim Van Sebroeck <wim@iguana.be>.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/ioport.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/kernel.h>
14*4882a593Smuzhiyun #include <linux/init.h>
15*4882a593Smuzhiyun #include <linux/platform_device.h>
16*4882a593Smuzhiyun #include <linux/gpio/driver.h>
17*4882a593Smuzhiyun #include <linux/bitops.h>
18*4882a593Smuzhiyun #include <linux/io.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define DRV_NAME "gpio-sch311x"
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #define SCH311X_GPIO_CONF_DIR BIT(0)
23*4882a593Smuzhiyun #define SCH311X_GPIO_CONF_INVERT BIT(1)
24*4882a593Smuzhiyun #define SCH311X_GPIO_CONF_OPEN_DRAIN BIT(7)
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define SIO_CONFIG_KEY_ENTER 0x55
27*4882a593Smuzhiyun #define SIO_CONFIG_KEY_EXIT 0xaa
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define GP1 0x4b
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun static int sch311x_ioports[] = { 0x2e, 0x4e, 0x162e, 0x164e };
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun static struct platform_device *sch311x_gpio_pdev;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun struct sch311x_pdev_data { /* platform device data */
36*4882a593Smuzhiyun unsigned short runtime_reg; /* runtime register base address */
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun struct sch311x_gpio_block { /* one GPIO block runtime data */
40*4882a593Smuzhiyun struct gpio_chip chip;
41*4882a593Smuzhiyun unsigned short data_reg; /* from definition below */
42*4882a593Smuzhiyun unsigned short *config_regs; /* pointer to definition below */
43*4882a593Smuzhiyun unsigned short runtime_reg; /* runtime register */
44*4882a593Smuzhiyun spinlock_t lock; /* lock for this GPIO block */
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun struct sch311x_gpio_priv { /* driver private data */
48*4882a593Smuzhiyun struct sch311x_gpio_block blocks[6];
49*4882a593Smuzhiyun };
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun struct sch311x_gpio_block_def { /* register address definitions */
52*4882a593Smuzhiyun unsigned short data_reg;
53*4882a593Smuzhiyun unsigned short config_regs[8];
54*4882a593Smuzhiyun unsigned short base;
55*4882a593Smuzhiyun };
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /* Note: some GPIOs are not available, these are marked with 0x00 */
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun static struct sch311x_gpio_block_def sch311x_gpio_blocks[] = {
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun .data_reg = 0x4b, /* GP1 */
62*4882a593Smuzhiyun .config_regs = {0x23, 0x24, 0x25, 0x26, 0x27, 0x29, 0x2a, 0x2b},
63*4882a593Smuzhiyun .base = 10,
64*4882a593Smuzhiyun },
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun .data_reg = 0x4c, /* GP2 */
67*4882a593Smuzhiyun .config_regs = {0x00, 0x2c, 0x2d, 0x00, 0x00, 0x00, 0x00, 0x32},
68*4882a593Smuzhiyun .base = 20,
69*4882a593Smuzhiyun },
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun .data_reg = 0x4d, /* GP3 */
72*4882a593Smuzhiyun .config_regs = {0x33, 0x34, 0x35, 0x36, 0x37, 0x00, 0x39, 0x3a},
73*4882a593Smuzhiyun .base = 30,
74*4882a593Smuzhiyun },
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun .data_reg = 0x4e, /* GP4 */
77*4882a593Smuzhiyun .config_regs = {0x3b, 0x00, 0x3d, 0x00, 0x6e, 0x6f, 0x72, 0x73},
78*4882a593Smuzhiyun .base = 40,
79*4882a593Smuzhiyun },
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun .data_reg = 0x4f, /* GP5 */
82*4882a593Smuzhiyun .config_regs = {0x3f, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46},
83*4882a593Smuzhiyun .base = 50,
84*4882a593Smuzhiyun },
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun .data_reg = 0x50, /* GP6 */
87*4882a593Smuzhiyun .config_regs = {0x47, 0x48, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59},
88*4882a593Smuzhiyun .base = 60,
89*4882a593Smuzhiyun },
90*4882a593Smuzhiyun };
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun /*
93*4882a593Smuzhiyun * Super-IO functions
94*4882a593Smuzhiyun */
95*4882a593Smuzhiyun
sch311x_sio_enter(int sio_config_port)96*4882a593Smuzhiyun static inline int sch311x_sio_enter(int sio_config_port)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun /* Don't step on other drivers' I/O space by accident. */
99*4882a593Smuzhiyun if (!request_muxed_region(sio_config_port, 2, DRV_NAME)) {
100*4882a593Smuzhiyun pr_err(DRV_NAME "I/O address 0x%04x already in use\n",
101*4882a593Smuzhiyun sio_config_port);
102*4882a593Smuzhiyun return -EBUSY;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun outb(SIO_CONFIG_KEY_ENTER, sio_config_port);
106*4882a593Smuzhiyun return 0;
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
sch311x_sio_exit(int sio_config_port)109*4882a593Smuzhiyun static inline void sch311x_sio_exit(int sio_config_port)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun outb(SIO_CONFIG_KEY_EXIT, sio_config_port);
112*4882a593Smuzhiyun release_region(sio_config_port, 2);
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun
sch311x_sio_inb(int sio_config_port,int reg)115*4882a593Smuzhiyun static inline int sch311x_sio_inb(int sio_config_port, int reg)
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun outb(reg, sio_config_port);
118*4882a593Smuzhiyun return inb(sio_config_port + 1);
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
sch311x_sio_outb(int sio_config_port,int reg,int val)121*4882a593Smuzhiyun static inline void sch311x_sio_outb(int sio_config_port, int reg, int val)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun outb(reg, sio_config_port);
124*4882a593Smuzhiyun outb(val, sio_config_port + 1);
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun /*
129*4882a593Smuzhiyun * GPIO functions
130*4882a593Smuzhiyun */
131*4882a593Smuzhiyun
sch311x_gpio_request(struct gpio_chip * chip,unsigned offset)132*4882a593Smuzhiyun static int sch311x_gpio_request(struct gpio_chip *chip, unsigned offset)
133*4882a593Smuzhiyun {
134*4882a593Smuzhiyun struct sch311x_gpio_block *block = gpiochip_get_data(chip);
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun if (block->config_regs[offset] == 0) /* GPIO is not available */
137*4882a593Smuzhiyun return -ENODEV;
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun if (!request_region(block->runtime_reg + block->config_regs[offset],
140*4882a593Smuzhiyun 1, DRV_NAME)) {
141*4882a593Smuzhiyun dev_err(chip->parent, "Failed to request region 0x%04x.\n",
142*4882a593Smuzhiyun block->runtime_reg + block->config_regs[offset]);
143*4882a593Smuzhiyun return -EBUSY;
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun return 0;
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
sch311x_gpio_free(struct gpio_chip * chip,unsigned offset)148*4882a593Smuzhiyun static void sch311x_gpio_free(struct gpio_chip *chip, unsigned offset)
149*4882a593Smuzhiyun {
150*4882a593Smuzhiyun struct sch311x_gpio_block *block = gpiochip_get_data(chip);
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun if (block->config_regs[offset] == 0) /* GPIO is not available */
153*4882a593Smuzhiyun return;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun release_region(block->runtime_reg + block->config_regs[offset], 1);
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
sch311x_gpio_get(struct gpio_chip * chip,unsigned offset)158*4882a593Smuzhiyun static int sch311x_gpio_get(struct gpio_chip *chip, unsigned offset)
159*4882a593Smuzhiyun {
160*4882a593Smuzhiyun struct sch311x_gpio_block *block = gpiochip_get_data(chip);
161*4882a593Smuzhiyun u8 data;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun spin_lock(&block->lock);
164*4882a593Smuzhiyun data = inb(block->runtime_reg + block->data_reg);
165*4882a593Smuzhiyun spin_unlock(&block->lock);
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun return !!(data & BIT(offset));
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun
__sch311x_gpio_set(struct sch311x_gpio_block * block,unsigned offset,int value)170*4882a593Smuzhiyun static void __sch311x_gpio_set(struct sch311x_gpio_block *block,
171*4882a593Smuzhiyun unsigned offset, int value)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun u8 data = inb(block->runtime_reg + block->data_reg);
174*4882a593Smuzhiyun if (value)
175*4882a593Smuzhiyun data |= BIT(offset);
176*4882a593Smuzhiyun else
177*4882a593Smuzhiyun data &= ~BIT(offset);
178*4882a593Smuzhiyun outb(data, block->runtime_reg + block->data_reg);
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun
sch311x_gpio_set(struct gpio_chip * chip,unsigned offset,int value)181*4882a593Smuzhiyun static void sch311x_gpio_set(struct gpio_chip *chip, unsigned offset,
182*4882a593Smuzhiyun int value)
183*4882a593Smuzhiyun {
184*4882a593Smuzhiyun struct sch311x_gpio_block *block = gpiochip_get_data(chip);
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun spin_lock(&block->lock);
187*4882a593Smuzhiyun __sch311x_gpio_set(block, offset, value);
188*4882a593Smuzhiyun spin_unlock(&block->lock);
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun
sch311x_gpio_direction_in(struct gpio_chip * chip,unsigned offset)191*4882a593Smuzhiyun static int sch311x_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
192*4882a593Smuzhiyun {
193*4882a593Smuzhiyun struct sch311x_gpio_block *block = gpiochip_get_data(chip);
194*4882a593Smuzhiyun u8 data;
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun spin_lock(&block->lock);
197*4882a593Smuzhiyun data = inb(block->runtime_reg + block->config_regs[offset]);
198*4882a593Smuzhiyun data |= SCH311X_GPIO_CONF_DIR;
199*4882a593Smuzhiyun outb(data, block->runtime_reg + block->config_regs[offset]);
200*4882a593Smuzhiyun spin_unlock(&block->lock);
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun return 0;
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun
sch311x_gpio_direction_out(struct gpio_chip * chip,unsigned offset,int value)205*4882a593Smuzhiyun static int sch311x_gpio_direction_out(struct gpio_chip *chip, unsigned offset,
206*4882a593Smuzhiyun int value)
207*4882a593Smuzhiyun {
208*4882a593Smuzhiyun struct sch311x_gpio_block *block = gpiochip_get_data(chip);
209*4882a593Smuzhiyun u8 data;
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun spin_lock(&block->lock);
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun data = inb(block->runtime_reg + block->config_regs[offset]);
214*4882a593Smuzhiyun data &= ~SCH311X_GPIO_CONF_DIR;
215*4882a593Smuzhiyun outb(data, block->runtime_reg + block->config_regs[offset]);
216*4882a593Smuzhiyun __sch311x_gpio_set(block, offset, value);
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun spin_unlock(&block->lock);
219*4882a593Smuzhiyun return 0;
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun
sch311x_gpio_get_direction(struct gpio_chip * chip,unsigned offset)222*4882a593Smuzhiyun static int sch311x_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
223*4882a593Smuzhiyun {
224*4882a593Smuzhiyun struct sch311x_gpio_block *block = gpiochip_get_data(chip);
225*4882a593Smuzhiyun u8 data;
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun spin_lock(&block->lock);
228*4882a593Smuzhiyun data = inb(block->runtime_reg + block->config_regs[offset]);
229*4882a593Smuzhiyun spin_unlock(&block->lock);
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun if (data & SCH311X_GPIO_CONF_DIR)
232*4882a593Smuzhiyun return GPIO_LINE_DIRECTION_IN;
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun return GPIO_LINE_DIRECTION_OUT;
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun
sch311x_gpio_set_config(struct gpio_chip * chip,unsigned offset,unsigned long config)237*4882a593Smuzhiyun static int sch311x_gpio_set_config(struct gpio_chip *chip, unsigned offset,
238*4882a593Smuzhiyun unsigned long config)
239*4882a593Smuzhiyun {
240*4882a593Smuzhiyun struct sch311x_gpio_block *block = gpiochip_get_data(chip);
241*4882a593Smuzhiyun enum pin_config_param param = pinconf_to_config_param(config);
242*4882a593Smuzhiyun u8 data;
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun switch (param) {
245*4882a593Smuzhiyun case PIN_CONFIG_DRIVE_OPEN_DRAIN:
246*4882a593Smuzhiyun spin_lock(&block->lock);
247*4882a593Smuzhiyun data = inb(block->runtime_reg + block->config_regs[offset]);
248*4882a593Smuzhiyun data |= SCH311X_GPIO_CONF_OPEN_DRAIN;
249*4882a593Smuzhiyun outb(data, block->runtime_reg + block->config_regs[offset]);
250*4882a593Smuzhiyun spin_unlock(&block->lock);
251*4882a593Smuzhiyun return 0;
252*4882a593Smuzhiyun case PIN_CONFIG_DRIVE_PUSH_PULL:
253*4882a593Smuzhiyun spin_lock(&block->lock);
254*4882a593Smuzhiyun data = inb(block->runtime_reg + block->config_regs[offset]);
255*4882a593Smuzhiyun data &= ~SCH311X_GPIO_CONF_OPEN_DRAIN;
256*4882a593Smuzhiyun outb(data, block->runtime_reg + block->config_regs[offset]);
257*4882a593Smuzhiyun spin_unlock(&block->lock);
258*4882a593Smuzhiyun return 0;
259*4882a593Smuzhiyun default:
260*4882a593Smuzhiyun break;
261*4882a593Smuzhiyun }
262*4882a593Smuzhiyun return -ENOTSUPP;
263*4882a593Smuzhiyun }
264*4882a593Smuzhiyun
sch311x_gpio_probe(struct platform_device * pdev)265*4882a593Smuzhiyun static int sch311x_gpio_probe(struct platform_device *pdev)
266*4882a593Smuzhiyun {
267*4882a593Smuzhiyun struct sch311x_pdev_data *pdata = dev_get_platdata(&pdev->dev);
268*4882a593Smuzhiyun struct sch311x_gpio_priv *priv;
269*4882a593Smuzhiyun struct sch311x_gpio_block *block;
270*4882a593Smuzhiyun int err, i;
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun /* we can register all GPIO data registers at once */
273*4882a593Smuzhiyun if (!devm_request_region(&pdev->dev, pdata->runtime_reg + GP1, 6,
274*4882a593Smuzhiyun DRV_NAME)) {
275*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to request region 0x%04x-0x%04x.\n",
276*4882a593Smuzhiyun pdata->runtime_reg + GP1, pdata->runtime_reg + GP1 + 5);
277*4882a593Smuzhiyun return -EBUSY;
278*4882a593Smuzhiyun }
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
281*4882a593Smuzhiyun if (!priv)
282*4882a593Smuzhiyun return -ENOMEM;
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun platform_set_drvdata(pdev, priv);
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(priv->blocks); i++) {
287*4882a593Smuzhiyun block = &priv->blocks[i];
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun spin_lock_init(&block->lock);
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun block->chip.label = DRV_NAME;
292*4882a593Smuzhiyun block->chip.owner = THIS_MODULE;
293*4882a593Smuzhiyun block->chip.request = sch311x_gpio_request;
294*4882a593Smuzhiyun block->chip.free = sch311x_gpio_free;
295*4882a593Smuzhiyun block->chip.direction_input = sch311x_gpio_direction_in;
296*4882a593Smuzhiyun block->chip.direction_output = sch311x_gpio_direction_out;
297*4882a593Smuzhiyun block->chip.get_direction = sch311x_gpio_get_direction;
298*4882a593Smuzhiyun block->chip.set_config = sch311x_gpio_set_config;
299*4882a593Smuzhiyun block->chip.get = sch311x_gpio_get;
300*4882a593Smuzhiyun block->chip.set = sch311x_gpio_set;
301*4882a593Smuzhiyun block->chip.ngpio = 8;
302*4882a593Smuzhiyun block->chip.parent = &pdev->dev;
303*4882a593Smuzhiyun block->chip.base = sch311x_gpio_blocks[i].base;
304*4882a593Smuzhiyun block->config_regs = sch311x_gpio_blocks[i].config_regs;
305*4882a593Smuzhiyun block->data_reg = sch311x_gpio_blocks[i].data_reg;
306*4882a593Smuzhiyun block->runtime_reg = pdata->runtime_reg;
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun err = gpiochip_add_data(&block->chip, block);
309*4882a593Smuzhiyun if (err < 0) {
310*4882a593Smuzhiyun dev_err(&pdev->dev,
311*4882a593Smuzhiyun "Could not register gpiochip, %d\n", err);
312*4882a593Smuzhiyun goto exit_err;
313*4882a593Smuzhiyun }
314*4882a593Smuzhiyun dev_info(&pdev->dev,
315*4882a593Smuzhiyun "SMSC SCH311x GPIO block %d registered.\n", i);
316*4882a593Smuzhiyun }
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun return 0;
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun exit_err:
321*4882a593Smuzhiyun /* release already registered chips */
322*4882a593Smuzhiyun for (--i; i >= 0; i--)
323*4882a593Smuzhiyun gpiochip_remove(&priv->blocks[i].chip);
324*4882a593Smuzhiyun return err;
325*4882a593Smuzhiyun }
326*4882a593Smuzhiyun
sch311x_gpio_remove(struct platform_device * pdev)327*4882a593Smuzhiyun static int sch311x_gpio_remove(struct platform_device *pdev)
328*4882a593Smuzhiyun {
329*4882a593Smuzhiyun struct sch311x_gpio_priv *priv = platform_get_drvdata(pdev);
330*4882a593Smuzhiyun int i;
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(priv->blocks); i++) {
333*4882a593Smuzhiyun gpiochip_remove(&priv->blocks[i].chip);
334*4882a593Smuzhiyun dev_info(&pdev->dev,
335*4882a593Smuzhiyun "SMSC SCH311x GPIO block %d unregistered.\n", i);
336*4882a593Smuzhiyun }
337*4882a593Smuzhiyun return 0;
338*4882a593Smuzhiyun }
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun static struct platform_driver sch311x_gpio_driver = {
341*4882a593Smuzhiyun .driver.name = DRV_NAME,
342*4882a593Smuzhiyun .probe = sch311x_gpio_probe,
343*4882a593Smuzhiyun .remove = sch311x_gpio_remove,
344*4882a593Smuzhiyun };
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun /*
348*4882a593Smuzhiyun * Init & exit routines
349*4882a593Smuzhiyun */
350*4882a593Smuzhiyun
sch311x_detect(int sio_config_port,unsigned short * addr)351*4882a593Smuzhiyun static int __init sch311x_detect(int sio_config_port, unsigned short *addr)
352*4882a593Smuzhiyun {
353*4882a593Smuzhiyun int err = 0, reg;
354*4882a593Smuzhiyun unsigned short base_addr;
355*4882a593Smuzhiyun u8 dev_id;
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun err = sch311x_sio_enter(sio_config_port);
358*4882a593Smuzhiyun if (err)
359*4882a593Smuzhiyun return err;
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun /* Check device ID. */
362*4882a593Smuzhiyun reg = sch311x_sio_inb(sio_config_port, 0x20);
363*4882a593Smuzhiyun switch (reg) {
364*4882a593Smuzhiyun case 0x7c: /* SCH3112 */
365*4882a593Smuzhiyun dev_id = 2;
366*4882a593Smuzhiyun break;
367*4882a593Smuzhiyun case 0x7d: /* SCH3114 */
368*4882a593Smuzhiyun dev_id = 4;
369*4882a593Smuzhiyun break;
370*4882a593Smuzhiyun case 0x7f: /* SCH3116 */
371*4882a593Smuzhiyun dev_id = 6;
372*4882a593Smuzhiyun break;
373*4882a593Smuzhiyun default:
374*4882a593Smuzhiyun err = -ENODEV;
375*4882a593Smuzhiyun goto exit;
376*4882a593Smuzhiyun }
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun /* Select logical device A (runtime registers) */
379*4882a593Smuzhiyun sch311x_sio_outb(sio_config_port, 0x07, 0x0a);
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun /* Check if Logical Device Register is currently active */
382*4882a593Smuzhiyun if ((sch311x_sio_inb(sio_config_port, 0x30) & 0x01) == 0)
383*4882a593Smuzhiyun pr_info("Seems that LDN 0x0a is not active...\n");
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun /* Get the base address of the runtime registers */
386*4882a593Smuzhiyun base_addr = (sch311x_sio_inb(sio_config_port, 0x60) << 8) |
387*4882a593Smuzhiyun sch311x_sio_inb(sio_config_port, 0x61);
388*4882a593Smuzhiyun if (!base_addr) {
389*4882a593Smuzhiyun pr_err("Base address not set\n");
390*4882a593Smuzhiyun err = -ENODEV;
391*4882a593Smuzhiyun goto exit;
392*4882a593Smuzhiyun }
393*4882a593Smuzhiyun *addr = base_addr;
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun pr_info("Found an SMSC SCH311%d chip at 0x%04x\n", dev_id, base_addr);
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun exit:
398*4882a593Smuzhiyun sch311x_sio_exit(sio_config_port);
399*4882a593Smuzhiyun return err;
400*4882a593Smuzhiyun }
401*4882a593Smuzhiyun
sch311x_gpio_pdev_add(const unsigned short addr)402*4882a593Smuzhiyun static int __init sch311x_gpio_pdev_add(const unsigned short addr)
403*4882a593Smuzhiyun {
404*4882a593Smuzhiyun struct sch311x_pdev_data pdata;
405*4882a593Smuzhiyun int err;
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun pdata.runtime_reg = addr;
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun sch311x_gpio_pdev = platform_device_alloc(DRV_NAME, -1);
410*4882a593Smuzhiyun if (!sch311x_gpio_pdev)
411*4882a593Smuzhiyun return -ENOMEM;
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun err = platform_device_add_data(sch311x_gpio_pdev,
414*4882a593Smuzhiyun &pdata, sizeof(pdata));
415*4882a593Smuzhiyun if (err) {
416*4882a593Smuzhiyun pr_err(DRV_NAME "Platform data allocation failed\n");
417*4882a593Smuzhiyun goto err;
418*4882a593Smuzhiyun }
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun err = platform_device_add(sch311x_gpio_pdev);
421*4882a593Smuzhiyun if (err) {
422*4882a593Smuzhiyun pr_err(DRV_NAME "Device addition failed\n");
423*4882a593Smuzhiyun goto err;
424*4882a593Smuzhiyun }
425*4882a593Smuzhiyun return 0;
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun err:
428*4882a593Smuzhiyun platform_device_put(sch311x_gpio_pdev);
429*4882a593Smuzhiyun return err;
430*4882a593Smuzhiyun }
431*4882a593Smuzhiyun
sch311x_gpio_init(void)432*4882a593Smuzhiyun static int __init sch311x_gpio_init(void)
433*4882a593Smuzhiyun {
434*4882a593Smuzhiyun int err, i;
435*4882a593Smuzhiyun unsigned short addr = 0;
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(sch311x_ioports); i++)
438*4882a593Smuzhiyun if (sch311x_detect(sch311x_ioports[i], &addr) == 0)
439*4882a593Smuzhiyun break;
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun if (!addr)
442*4882a593Smuzhiyun return -ENODEV;
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun err = platform_driver_register(&sch311x_gpio_driver);
445*4882a593Smuzhiyun if (err)
446*4882a593Smuzhiyun return err;
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun err = sch311x_gpio_pdev_add(addr);
449*4882a593Smuzhiyun if (err)
450*4882a593Smuzhiyun goto unreg_platform_driver;
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun return 0;
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun unreg_platform_driver:
455*4882a593Smuzhiyun platform_driver_unregister(&sch311x_gpio_driver);
456*4882a593Smuzhiyun return err;
457*4882a593Smuzhiyun }
458*4882a593Smuzhiyun
sch311x_gpio_exit(void)459*4882a593Smuzhiyun static void __exit sch311x_gpio_exit(void)
460*4882a593Smuzhiyun {
461*4882a593Smuzhiyun platform_device_unregister(sch311x_gpio_pdev);
462*4882a593Smuzhiyun platform_driver_unregister(&sch311x_gpio_driver);
463*4882a593Smuzhiyun }
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun module_init(sch311x_gpio_init);
466*4882a593Smuzhiyun module_exit(sch311x_gpio_exit);
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun MODULE_AUTHOR("Bruno Randolf <br1@einfach.org>");
469*4882a593Smuzhiyun MODULE_DESCRIPTION("SMSC SCH311x GPIO Driver");
470*4882a593Smuzhiyun MODULE_LICENSE("GPL");
471*4882a593Smuzhiyun MODULE_ALIAS("platform:gpio-sch311x");
472