1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * RDC321x GPIO driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2008, Volker Weiss <dev@tintuc.de>
6*4882a593Smuzhiyun * Copyright (C) 2007-2010 Florian Fainelli <florian@openwrt.org>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/kernel.h>
10*4882a593Smuzhiyun #include <linux/init.h>
11*4882a593Smuzhiyun #include <linux/spinlock.h>
12*4882a593Smuzhiyun #include <linux/platform_device.h>
13*4882a593Smuzhiyun #include <linux/pci.h>
14*4882a593Smuzhiyun #include <linux/gpio/driver.h>
15*4882a593Smuzhiyun #include <linux/mfd/rdc321x.h>
16*4882a593Smuzhiyun #include <linux/slab.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun struct rdc321x_gpio {
19*4882a593Smuzhiyun spinlock_t lock;
20*4882a593Smuzhiyun struct pci_dev *sb_pdev;
21*4882a593Smuzhiyun u32 data_reg[2];
22*4882a593Smuzhiyun int reg1_ctrl_base;
23*4882a593Smuzhiyun int reg1_data_base;
24*4882a593Smuzhiyun int reg2_ctrl_base;
25*4882a593Smuzhiyun int reg2_data_base;
26*4882a593Smuzhiyun struct gpio_chip chip;
27*4882a593Smuzhiyun };
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /* read GPIO pin */
rdc_gpio_get_value(struct gpio_chip * chip,unsigned gpio)30*4882a593Smuzhiyun static int rdc_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun struct rdc321x_gpio *gpch;
33*4882a593Smuzhiyun u32 value = 0;
34*4882a593Smuzhiyun int reg;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun gpch = gpiochip_get_data(chip);
37*4882a593Smuzhiyun reg = gpio < 32 ? gpch->reg1_data_base : gpch->reg2_data_base;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun spin_lock(&gpch->lock);
40*4882a593Smuzhiyun pci_write_config_dword(gpch->sb_pdev, reg,
41*4882a593Smuzhiyun gpch->data_reg[gpio < 32 ? 0 : 1]);
42*4882a593Smuzhiyun pci_read_config_dword(gpch->sb_pdev, reg, &value);
43*4882a593Smuzhiyun spin_unlock(&gpch->lock);
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun return (1 << (gpio & 0x1f)) & value ? 1 : 0;
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
rdc_gpio_set_value_impl(struct gpio_chip * chip,unsigned gpio,int value)48*4882a593Smuzhiyun static void rdc_gpio_set_value_impl(struct gpio_chip *chip,
49*4882a593Smuzhiyun unsigned gpio, int value)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun struct rdc321x_gpio *gpch;
52*4882a593Smuzhiyun int reg = (gpio < 32) ? 0 : 1;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun gpch = gpiochip_get_data(chip);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun if (value)
57*4882a593Smuzhiyun gpch->data_reg[reg] |= 1 << (gpio & 0x1f);
58*4882a593Smuzhiyun else
59*4882a593Smuzhiyun gpch->data_reg[reg] &= ~(1 << (gpio & 0x1f));
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun pci_write_config_dword(gpch->sb_pdev,
62*4882a593Smuzhiyun reg ? gpch->reg2_data_base : gpch->reg1_data_base,
63*4882a593Smuzhiyun gpch->data_reg[reg]);
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun /* set GPIO pin to value */
rdc_gpio_set_value(struct gpio_chip * chip,unsigned gpio,int value)67*4882a593Smuzhiyun static void rdc_gpio_set_value(struct gpio_chip *chip,
68*4882a593Smuzhiyun unsigned gpio, int value)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun struct rdc321x_gpio *gpch;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun gpch = gpiochip_get_data(chip);
73*4882a593Smuzhiyun spin_lock(&gpch->lock);
74*4882a593Smuzhiyun rdc_gpio_set_value_impl(chip, gpio, value);
75*4882a593Smuzhiyun spin_unlock(&gpch->lock);
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
rdc_gpio_config(struct gpio_chip * chip,unsigned gpio,int value)78*4882a593Smuzhiyun static int rdc_gpio_config(struct gpio_chip *chip,
79*4882a593Smuzhiyun unsigned gpio, int value)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun struct rdc321x_gpio *gpch;
82*4882a593Smuzhiyun int err;
83*4882a593Smuzhiyun u32 reg;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun gpch = gpiochip_get_data(chip);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun spin_lock(&gpch->lock);
88*4882a593Smuzhiyun err = pci_read_config_dword(gpch->sb_pdev, gpio < 32 ?
89*4882a593Smuzhiyun gpch->reg1_ctrl_base : gpch->reg2_ctrl_base, ®);
90*4882a593Smuzhiyun if (err)
91*4882a593Smuzhiyun goto unlock;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun reg |= 1 << (gpio & 0x1f);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun err = pci_write_config_dword(gpch->sb_pdev, gpio < 32 ?
96*4882a593Smuzhiyun gpch->reg1_ctrl_base : gpch->reg2_ctrl_base, reg);
97*4882a593Smuzhiyun if (err)
98*4882a593Smuzhiyun goto unlock;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun rdc_gpio_set_value_impl(chip, gpio, value);
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun unlock:
103*4882a593Smuzhiyun spin_unlock(&gpch->lock);
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun return err;
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun /* configure GPIO pin as input */
rdc_gpio_direction_input(struct gpio_chip * chip,unsigned gpio)109*4882a593Smuzhiyun static int rdc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun return rdc_gpio_config(chip, gpio, 1);
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /*
115*4882a593Smuzhiyun * Cache the initial value of both GPIO data registers
116*4882a593Smuzhiyun */
rdc321x_gpio_probe(struct platform_device * pdev)117*4882a593Smuzhiyun static int rdc321x_gpio_probe(struct platform_device *pdev)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun int err;
120*4882a593Smuzhiyun struct resource *r;
121*4882a593Smuzhiyun struct rdc321x_gpio *rdc321x_gpio_dev;
122*4882a593Smuzhiyun struct rdc321x_gpio_pdata *pdata;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun pdata = dev_get_platdata(&pdev->dev);
125*4882a593Smuzhiyun if (!pdata) {
126*4882a593Smuzhiyun dev_err(&pdev->dev, "no platform data supplied\n");
127*4882a593Smuzhiyun return -ENODEV;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun rdc321x_gpio_dev = devm_kzalloc(&pdev->dev, sizeof(struct rdc321x_gpio),
131*4882a593Smuzhiyun GFP_KERNEL);
132*4882a593Smuzhiyun if (!rdc321x_gpio_dev)
133*4882a593Smuzhiyun return -ENOMEM;
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun r = platform_get_resource_byname(pdev, IORESOURCE_IO, "gpio-reg1");
136*4882a593Smuzhiyun if (!r) {
137*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to get gpio-reg1 resource\n");
138*4882a593Smuzhiyun return -ENODEV;
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun spin_lock_init(&rdc321x_gpio_dev->lock);
142*4882a593Smuzhiyun rdc321x_gpio_dev->sb_pdev = pdata->sb_pdev;
143*4882a593Smuzhiyun rdc321x_gpio_dev->reg1_ctrl_base = r->start;
144*4882a593Smuzhiyun rdc321x_gpio_dev->reg1_data_base = r->start + 0x4;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun r = platform_get_resource_byname(pdev, IORESOURCE_IO, "gpio-reg2");
147*4882a593Smuzhiyun if (!r) {
148*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to get gpio-reg2 resource\n");
149*4882a593Smuzhiyun return -ENODEV;
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun rdc321x_gpio_dev->reg2_ctrl_base = r->start;
153*4882a593Smuzhiyun rdc321x_gpio_dev->reg2_data_base = r->start + 0x4;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun rdc321x_gpio_dev->chip.label = "rdc321x-gpio";
156*4882a593Smuzhiyun rdc321x_gpio_dev->chip.owner = THIS_MODULE;
157*4882a593Smuzhiyun rdc321x_gpio_dev->chip.direction_input = rdc_gpio_direction_input;
158*4882a593Smuzhiyun rdc321x_gpio_dev->chip.direction_output = rdc_gpio_config;
159*4882a593Smuzhiyun rdc321x_gpio_dev->chip.get = rdc_gpio_get_value;
160*4882a593Smuzhiyun rdc321x_gpio_dev->chip.set = rdc_gpio_set_value;
161*4882a593Smuzhiyun rdc321x_gpio_dev->chip.base = 0;
162*4882a593Smuzhiyun rdc321x_gpio_dev->chip.ngpio = pdata->max_gpios;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun platform_set_drvdata(pdev, rdc321x_gpio_dev);
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun /* This might not be, what others (BIOS, bootloader, etc.)
167*4882a593Smuzhiyun wrote to these registers before, but it's a good guess. Still
168*4882a593Smuzhiyun better than just using 0xffffffff. */
169*4882a593Smuzhiyun err = pci_read_config_dword(rdc321x_gpio_dev->sb_pdev,
170*4882a593Smuzhiyun rdc321x_gpio_dev->reg1_data_base,
171*4882a593Smuzhiyun &rdc321x_gpio_dev->data_reg[0]);
172*4882a593Smuzhiyun if (err)
173*4882a593Smuzhiyun return err;
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun err = pci_read_config_dword(rdc321x_gpio_dev->sb_pdev,
176*4882a593Smuzhiyun rdc321x_gpio_dev->reg2_data_base,
177*4882a593Smuzhiyun &rdc321x_gpio_dev->data_reg[1]);
178*4882a593Smuzhiyun if (err)
179*4882a593Smuzhiyun return err;
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun dev_info(&pdev->dev, "registering %d GPIOs\n",
182*4882a593Smuzhiyun rdc321x_gpio_dev->chip.ngpio);
183*4882a593Smuzhiyun return devm_gpiochip_add_data(&pdev->dev, &rdc321x_gpio_dev->chip,
184*4882a593Smuzhiyun rdc321x_gpio_dev);
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun static struct platform_driver rdc321x_gpio_driver = {
188*4882a593Smuzhiyun .driver.name = "rdc321x-gpio",
189*4882a593Smuzhiyun .probe = rdc321x_gpio_probe,
190*4882a593Smuzhiyun };
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun module_platform_driver(rdc321x_gpio_driver);
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
195*4882a593Smuzhiyun MODULE_DESCRIPTION("RDC321x GPIO driver");
196*4882a593Smuzhiyun MODULE_LICENSE("GPL");
197*4882a593Smuzhiyun MODULE_ALIAS("platform:rdc321x-gpio");
198