1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
3*4882a593Smuzhiyun * Andrew F. Davis <afd@ti.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or
6*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License version 2 as
7*4882a593Smuzhiyun * published by the Free Software Foundation.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * This program is distributed "as is" WITHOUT ANY WARRANTY of any
10*4882a593Smuzhiyun * kind, whether expressed or implied; without even the implied warranty
11*4882a593Smuzhiyun * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12*4882a593Smuzhiyun * GNU General Public License version 2 for more details.
13*4882a593Smuzhiyun */
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <linux/bitmap.h>
16*4882a593Smuzhiyun #include <linux/bitops.h>
17*4882a593Smuzhiyun #include <linux/delay.h>
18*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
19*4882a593Smuzhiyun #include <linux/gpio/driver.h>
20*4882a593Smuzhiyun #include <linux/module.h>
21*4882a593Smuzhiyun #include <linux/mutex.h>
22*4882a593Smuzhiyun #include <linux/spi/spi.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define DEFAULT_NGPIO 8
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /**
27*4882a593Smuzhiyun * struct pisosr_gpio - GPIO driver data
28*4882a593Smuzhiyun * @chip: GPIO controller chip
29*4882a593Smuzhiyun * @spi: SPI device pointer
30*4882a593Smuzhiyun * @buffer: Buffer for device reads
31*4882a593Smuzhiyun * @buffer_size: Size of buffer
32*4882a593Smuzhiyun * @load_gpio: GPIO pin used to load input into device
33*4882a593Smuzhiyun * @lock: Protects read sequences
34*4882a593Smuzhiyun */
35*4882a593Smuzhiyun struct pisosr_gpio {
36*4882a593Smuzhiyun struct gpio_chip chip;
37*4882a593Smuzhiyun struct spi_device *spi;
38*4882a593Smuzhiyun u8 *buffer;
39*4882a593Smuzhiyun size_t buffer_size;
40*4882a593Smuzhiyun struct gpio_desc *load_gpio;
41*4882a593Smuzhiyun struct mutex lock;
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun
pisosr_gpio_refresh(struct pisosr_gpio * gpio)44*4882a593Smuzhiyun static int pisosr_gpio_refresh(struct pisosr_gpio *gpio)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun int ret;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun mutex_lock(&gpio->lock);
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun if (gpio->load_gpio) {
51*4882a593Smuzhiyun gpiod_set_value_cansleep(gpio->load_gpio, 1);
52*4882a593Smuzhiyun udelay(1); /* registers load time (~10ns) */
53*4882a593Smuzhiyun gpiod_set_value_cansleep(gpio->load_gpio, 0);
54*4882a593Smuzhiyun udelay(1); /* registers recovery time (~5ns) */
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun ret = spi_read(gpio->spi, gpio->buffer, gpio->buffer_size);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun mutex_unlock(&gpio->lock);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun return ret;
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
pisosr_gpio_get_direction(struct gpio_chip * chip,unsigned offset)64*4882a593Smuzhiyun static int pisosr_gpio_get_direction(struct gpio_chip *chip,
65*4882a593Smuzhiyun unsigned offset)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun /* This device always input */
68*4882a593Smuzhiyun return GPIO_LINE_DIRECTION_IN;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
pisosr_gpio_direction_input(struct gpio_chip * chip,unsigned offset)71*4882a593Smuzhiyun static int pisosr_gpio_direction_input(struct gpio_chip *chip,
72*4882a593Smuzhiyun unsigned offset)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun /* This device always input */
75*4882a593Smuzhiyun return 0;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
pisosr_gpio_direction_output(struct gpio_chip * chip,unsigned offset,int value)78*4882a593Smuzhiyun static int pisosr_gpio_direction_output(struct gpio_chip *chip,
79*4882a593Smuzhiyun unsigned offset, int value)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun /* This device is input only */
82*4882a593Smuzhiyun return -EINVAL;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
pisosr_gpio_get(struct gpio_chip * chip,unsigned offset)85*4882a593Smuzhiyun static int pisosr_gpio_get(struct gpio_chip *chip, unsigned offset)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun struct pisosr_gpio *gpio = gpiochip_get_data(chip);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun /* Refresh may not always be needed */
90*4882a593Smuzhiyun pisosr_gpio_refresh(gpio);
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun return (gpio->buffer[offset / 8] >> (offset % 8)) & 0x1;
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
pisosr_gpio_get_multiple(struct gpio_chip * chip,unsigned long * mask,unsigned long * bits)95*4882a593Smuzhiyun static int pisosr_gpio_get_multiple(struct gpio_chip *chip,
96*4882a593Smuzhiyun unsigned long *mask, unsigned long *bits)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun struct pisosr_gpio *gpio = gpiochip_get_data(chip);
99*4882a593Smuzhiyun unsigned long offset;
100*4882a593Smuzhiyun unsigned long gpio_mask;
101*4882a593Smuzhiyun unsigned long buffer_state;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun pisosr_gpio_refresh(gpio);
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun bitmap_zero(bits, chip->ngpio);
106*4882a593Smuzhiyun for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) {
107*4882a593Smuzhiyun buffer_state = gpio->buffer[offset / 8] & gpio_mask;
108*4882a593Smuzhiyun bitmap_set_value8(bits, buffer_state, offset);
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun return 0;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun static const struct gpio_chip template_chip = {
115*4882a593Smuzhiyun .label = "pisosr-gpio",
116*4882a593Smuzhiyun .owner = THIS_MODULE,
117*4882a593Smuzhiyun .get_direction = pisosr_gpio_get_direction,
118*4882a593Smuzhiyun .direction_input = pisosr_gpio_direction_input,
119*4882a593Smuzhiyun .direction_output = pisosr_gpio_direction_output,
120*4882a593Smuzhiyun .get = pisosr_gpio_get,
121*4882a593Smuzhiyun .get_multiple = pisosr_gpio_get_multiple,
122*4882a593Smuzhiyun .base = -1,
123*4882a593Smuzhiyun .ngpio = DEFAULT_NGPIO,
124*4882a593Smuzhiyun .can_sleep = true,
125*4882a593Smuzhiyun };
126*4882a593Smuzhiyun
pisosr_gpio_probe(struct spi_device * spi)127*4882a593Smuzhiyun static int pisosr_gpio_probe(struct spi_device *spi)
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun struct device *dev = &spi->dev;
130*4882a593Smuzhiyun struct pisosr_gpio *gpio;
131*4882a593Smuzhiyun int ret;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun gpio = devm_kzalloc(dev, sizeof(*gpio), GFP_KERNEL);
134*4882a593Smuzhiyun if (!gpio)
135*4882a593Smuzhiyun return -ENOMEM;
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun spi_set_drvdata(spi, gpio);
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun gpio->chip = template_chip;
140*4882a593Smuzhiyun gpio->chip.parent = dev;
141*4882a593Smuzhiyun of_property_read_u16(dev->of_node, "ngpios", &gpio->chip.ngpio);
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun gpio->spi = spi;
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun gpio->buffer_size = DIV_ROUND_UP(gpio->chip.ngpio, 8);
146*4882a593Smuzhiyun gpio->buffer = devm_kzalloc(dev, gpio->buffer_size, GFP_KERNEL);
147*4882a593Smuzhiyun if (!gpio->buffer)
148*4882a593Smuzhiyun return -ENOMEM;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun gpio->load_gpio = devm_gpiod_get_optional(dev, "load", GPIOD_OUT_LOW);
151*4882a593Smuzhiyun if (IS_ERR(gpio->load_gpio))
152*4882a593Smuzhiyun return dev_err_probe(dev, PTR_ERR(gpio->load_gpio),
153*4882a593Smuzhiyun "Unable to allocate load GPIO\n");
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun mutex_init(&gpio->lock);
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun ret = gpiochip_add_data(&gpio->chip, gpio);
158*4882a593Smuzhiyun if (ret < 0) {
159*4882a593Smuzhiyun dev_err(dev, "Unable to register gpiochip\n");
160*4882a593Smuzhiyun return ret;
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun return 0;
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun
pisosr_gpio_remove(struct spi_device * spi)166*4882a593Smuzhiyun static int pisosr_gpio_remove(struct spi_device *spi)
167*4882a593Smuzhiyun {
168*4882a593Smuzhiyun struct pisosr_gpio *gpio = spi_get_drvdata(spi);
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun gpiochip_remove(&gpio->chip);
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun mutex_destroy(&gpio->lock);
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun return 0;
175*4882a593Smuzhiyun }
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun static const struct spi_device_id pisosr_gpio_id_table[] = {
178*4882a593Smuzhiyun { "pisosr-gpio", },
179*4882a593Smuzhiyun { /* sentinel */ }
180*4882a593Smuzhiyun };
181*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, pisosr_gpio_id_table);
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun static const struct of_device_id pisosr_gpio_of_match_table[] = {
184*4882a593Smuzhiyun { .compatible = "pisosr-gpio", },
185*4882a593Smuzhiyun { /* sentinel */ }
186*4882a593Smuzhiyun };
187*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, pisosr_gpio_of_match_table);
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun static struct spi_driver pisosr_gpio_driver = {
190*4882a593Smuzhiyun .driver = {
191*4882a593Smuzhiyun .name = "pisosr-gpio",
192*4882a593Smuzhiyun .of_match_table = pisosr_gpio_of_match_table,
193*4882a593Smuzhiyun },
194*4882a593Smuzhiyun .probe = pisosr_gpio_probe,
195*4882a593Smuzhiyun .remove = pisosr_gpio_remove,
196*4882a593Smuzhiyun .id_table = pisosr_gpio_id_table,
197*4882a593Smuzhiyun };
198*4882a593Smuzhiyun module_spi_driver(pisosr_gpio_driver);
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>");
201*4882a593Smuzhiyun MODULE_DESCRIPTION("SPI Compatible PISO Shift Register GPIO Driver");
202*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
203