1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * TI Palma series PMIC's GPIO driver.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Laxman Dewangan <ldewangan@nvidia.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/gpio/driver.h>
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/mfd/palmas.h>
14*4882a593Smuzhiyun #include <linux/of.h>
15*4882a593Smuzhiyun #include <linux/of_device.h>
16*4882a593Smuzhiyun #include <linux/platform_device.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun struct palmas_gpio {
19*4882a593Smuzhiyun struct gpio_chip gpio_chip;
20*4882a593Smuzhiyun struct palmas *palmas;
21*4882a593Smuzhiyun };
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun struct palmas_device_data {
24*4882a593Smuzhiyun int ngpio;
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun
palmas_gpio_get(struct gpio_chip * gc,unsigned offset)27*4882a593Smuzhiyun static int palmas_gpio_get(struct gpio_chip *gc, unsigned offset)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun struct palmas_gpio *pg = gpiochip_get_data(gc);
30*4882a593Smuzhiyun struct palmas *palmas = pg->palmas;
31*4882a593Smuzhiyun unsigned int val;
32*4882a593Smuzhiyun int ret;
33*4882a593Smuzhiyun unsigned int reg;
34*4882a593Smuzhiyun int gpio16 = (offset/8);
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun offset %= 8;
37*4882a593Smuzhiyun reg = (gpio16) ? PALMAS_GPIO_DATA_DIR2 : PALMAS_GPIO_DATA_DIR;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun ret = palmas_read(palmas, PALMAS_GPIO_BASE, reg, &val);
40*4882a593Smuzhiyun if (ret < 0) {
41*4882a593Smuzhiyun dev_err(gc->parent, "Reg 0x%02x read failed, %d\n", reg, ret);
42*4882a593Smuzhiyun return ret;
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun if (val & BIT(offset))
46*4882a593Smuzhiyun reg = (gpio16) ? PALMAS_GPIO_DATA_OUT2 : PALMAS_GPIO_DATA_OUT;
47*4882a593Smuzhiyun else
48*4882a593Smuzhiyun reg = (gpio16) ? PALMAS_GPIO_DATA_IN2 : PALMAS_GPIO_DATA_IN;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun ret = palmas_read(palmas, PALMAS_GPIO_BASE, reg, &val);
51*4882a593Smuzhiyun if (ret < 0) {
52*4882a593Smuzhiyun dev_err(gc->parent, "Reg 0x%02x read failed, %d\n", reg, ret);
53*4882a593Smuzhiyun return ret;
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun return !!(val & BIT(offset));
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun
palmas_gpio_set(struct gpio_chip * gc,unsigned offset,int value)58*4882a593Smuzhiyun static void palmas_gpio_set(struct gpio_chip *gc, unsigned offset,
59*4882a593Smuzhiyun int value)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun struct palmas_gpio *pg = gpiochip_get_data(gc);
62*4882a593Smuzhiyun struct palmas *palmas = pg->palmas;
63*4882a593Smuzhiyun int ret;
64*4882a593Smuzhiyun unsigned int reg;
65*4882a593Smuzhiyun int gpio16 = (offset/8);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun offset %= 8;
68*4882a593Smuzhiyun if (gpio16)
69*4882a593Smuzhiyun reg = (value) ?
70*4882a593Smuzhiyun PALMAS_GPIO_SET_DATA_OUT2 : PALMAS_GPIO_CLEAR_DATA_OUT2;
71*4882a593Smuzhiyun else
72*4882a593Smuzhiyun reg = (value) ?
73*4882a593Smuzhiyun PALMAS_GPIO_SET_DATA_OUT : PALMAS_GPIO_CLEAR_DATA_OUT;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun ret = palmas_write(palmas, PALMAS_GPIO_BASE, reg, BIT(offset));
76*4882a593Smuzhiyun if (ret < 0)
77*4882a593Smuzhiyun dev_err(gc->parent, "Reg 0x%02x write failed, %d\n", reg, ret);
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
palmas_gpio_output(struct gpio_chip * gc,unsigned offset,int value)80*4882a593Smuzhiyun static int palmas_gpio_output(struct gpio_chip *gc, unsigned offset,
81*4882a593Smuzhiyun int value)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun struct palmas_gpio *pg = gpiochip_get_data(gc);
84*4882a593Smuzhiyun struct palmas *palmas = pg->palmas;
85*4882a593Smuzhiyun int ret;
86*4882a593Smuzhiyun unsigned int reg;
87*4882a593Smuzhiyun int gpio16 = (offset/8);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun offset %= 8;
90*4882a593Smuzhiyun reg = (gpio16) ? PALMAS_GPIO_DATA_DIR2 : PALMAS_GPIO_DATA_DIR;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun /* Set the initial value */
93*4882a593Smuzhiyun palmas_gpio_set(gc, offset, value);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun ret = palmas_update_bits(palmas, PALMAS_GPIO_BASE, reg,
96*4882a593Smuzhiyun BIT(offset), BIT(offset));
97*4882a593Smuzhiyun if (ret < 0)
98*4882a593Smuzhiyun dev_err(gc->parent, "Reg 0x%02x update failed, %d\n", reg,
99*4882a593Smuzhiyun ret);
100*4882a593Smuzhiyun return ret;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
palmas_gpio_input(struct gpio_chip * gc,unsigned offset)103*4882a593Smuzhiyun static int palmas_gpio_input(struct gpio_chip *gc, unsigned offset)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun struct palmas_gpio *pg = gpiochip_get_data(gc);
106*4882a593Smuzhiyun struct palmas *palmas = pg->palmas;
107*4882a593Smuzhiyun int ret;
108*4882a593Smuzhiyun unsigned int reg;
109*4882a593Smuzhiyun int gpio16 = (offset/8);
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun offset %= 8;
112*4882a593Smuzhiyun reg = (gpio16) ? PALMAS_GPIO_DATA_DIR2 : PALMAS_GPIO_DATA_DIR;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun ret = palmas_update_bits(palmas, PALMAS_GPIO_BASE, reg, BIT(offset), 0);
115*4882a593Smuzhiyun if (ret < 0)
116*4882a593Smuzhiyun dev_err(gc->parent, "Reg 0x%02x update failed, %d\n", reg,
117*4882a593Smuzhiyun ret);
118*4882a593Smuzhiyun return ret;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
palmas_gpio_to_irq(struct gpio_chip * gc,unsigned offset)121*4882a593Smuzhiyun static int palmas_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun struct palmas_gpio *pg = gpiochip_get_data(gc);
124*4882a593Smuzhiyun struct palmas *palmas = pg->palmas;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun return palmas_irq_get_virq(palmas, PALMAS_GPIO_0_IRQ + offset);
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun static const struct palmas_device_data palmas_dev_data = {
130*4882a593Smuzhiyun .ngpio = 8,
131*4882a593Smuzhiyun };
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun static const struct palmas_device_data tps80036_dev_data = {
134*4882a593Smuzhiyun .ngpio = 16,
135*4882a593Smuzhiyun };
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun static const struct of_device_id of_palmas_gpio_match[] = {
138*4882a593Smuzhiyun { .compatible = "ti,palmas-gpio", .data = &palmas_dev_data,},
139*4882a593Smuzhiyun { .compatible = "ti,tps65913-gpio", .data = &palmas_dev_data,},
140*4882a593Smuzhiyun { .compatible = "ti,tps65914-gpio", .data = &palmas_dev_data,},
141*4882a593Smuzhiyun { .compatible = "ti,tps80036-gpio", .data = &tps80036_dev_data,},
142*4882a593Smuzhiyun { },
143*4882a593Smuzhiyun };
144*4882a593Smuzhiyun
palmas_gpio_probe(struct platform_device * pdev)145*4882a593Smuzhiyun static int palmas_gpio_probe(struct platform_device *pdev)
146*4882a593Smuzhiyun {
147*4882a593Smuzhiyun struct palmas *palmas = dev_get_drvdata(pdev->dev.parent);
148*4882a593Smuzhiyun struct palmas_platform_data *palmas_pdata;
149*4882a593Smuzhiyun struct palmas_gpio *palmas_gpio;
150*4882a593Smuzhiyun int ret;
151*4882a593Smuzhiyun const struct palmas_device_data *dev_data;
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun dev_data = of_device_get_match_data(&pdev->dev);
154*4882a593Smuzhiyun if (!dev_data)
155*4882a593Smuzhiyun dev_data = &palmas_dev_data;
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun palmas_gpio = devm_kzalloc(&pdev->dev,
158*4882a593Smuzhiyun sizeof(*palmas_gpio), GFP_KERNEL);
159*4882a593Smuzhiyun if (!palmas_gpio)
160*4882a593Smuzhiyun return -ENOMEM;
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun palmas_gpio->palmas = palmas;
163*4882a593Smuzhiyun palmas_gpio->gpio_chip.owner = THIS_MODULE;
164*4882a593Smuzhiyun palmas_gpio->gpio_chip.label = dev_name(&pdev->dev);
165*4882a593Smuzhiyun palmas_gpio->gpio_chip.ngpio = dev_data->ngpio;
166*4882a593Smuzhiyun palmas_gpio->gpio_chip.can_sleep = true;
167*4882a593Smuzhiyun palmas_gpio->gpio_chip.direction_input = palmas_gpio_input;
168*4882a593Smuzhiyun palmas_gpio->gpio_chip.direction_output = palmas_gpio_output;
169*4882a593Smuzhiyun palmas_gpio->gpio_chip.to_irq = palmas_gpio_to_irq;
170*4882a593Smuzhiyun palmas_gpio->gpio_chip.set = palmas_gpio_set;
171*4882a593Smuzhiyun palmas_gpio->gpio_chip.get = palmas_gpio_get;
172*4882a593Smuzhiyun palmas_gpio->gpio_chip.parent = &pdev->dev;
173*4882a593Smuzhiyun #ifdef CONFIG_OF_GPIO
174*4882a593Smuzhiyun palmas_gpio->gpio_chip.of_node = pdev->dev.of_node;
175*4882a593Smuzhiyun #endif
176*4882a593Smuzhiyun palmas_pdata = dev_get_platdata(palmas->dev);
177*4882a593Smuzhiyun if (palmas_pdata && palmas_pdata->gpio_base)
178*4882a593Smuzhiyun palmas_gpio->gpio_chip.base = palmas_pdata->gpio_base;
179*4882a593Smuzhiyun else
180*4882a593Smuzhiyun palmas_gpio->gpio_chip.base = -1;
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun ret = devm_gpiochip_add_data(&pdev->dev, &palmas_gpio->gpio_chip,
183*4882a593Smuzhiyun palmas_gpio);
184*4882a593Smuzhiyun if (ret < 0) {
185*4882a593Smuzhiyun dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret);
186*4882a593Smuzhiyun return ret;
187*4882a593Smuzhiyun }
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun platform_set_drvdata(pdev, palmas_gpio);
190*4882a593Smuzhiyun return ret;
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun static struct platform_driver palmas_gpio_driver = {
194*4882a593Smuzhiyun .driver.name = "palmas-gpio",
195*4882a593Smuzhiyun .driver.of_match_table = of_palmas_gpio_match,
196*4882a593Smuzhiyun .probe = palmas_gpio_probe,
197*4882a593Smuzhiyun };
198*4882a593Smuzhiyun
palmas_gpio_init(void)199*4882a593Smuzhiyun static int __init palmas_gpio_init(void)
200*4882a593Smuzhiyun {
201*4882a593Smuzhiyun return platform_driver_register(&palmas_gpio_driver);
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun subsys_initcall(palmas_gpio_init);
204