xref: /OK3568_Linux_fs/kernel/drivers/gpio/gpio-mm-lantiq.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  *  Copyright (C) 2012 John Crispin <john@phrozen.org>
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <linux/init.h>
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/types.h>
10*4882a593Smuzhiyun #include <linux/platform_device.h>
11*4882a593Smuzhiyun #include <linux/mutex.h>
12*4882a593Smuzhiyun #include <linux/gpio/driver.h>
13*4882a593Smuzhiyun #include <linux/of.h>
14*4882a593Smuzhiyun #include <linux/of_gpio.h>
15*4882a593Smuzhiyun #include <linux/io.h>
16*4882a593Smuzhiyun #include <linux/slab.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #include <lantiq_soc.h>
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun /*
21*4882a593Smuzhiyun  * By attaching hardware latches to the EBU it is possible to create output
22*4882a593Smuzhiyun  * only gpios. This driver configures a special memory address, which when
23*4882a593Smuzhiyun  * written to outputs 16 bit to the latches.
24*4882a593Smuzhiyun  */
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun #define LTQ_EBU_BUSCON	0x1e7ff		/* 16 bit access, slowest timing */
27*4882a593Smuzhiyun #define LTQ_EBU_WP	0x80000000	/* write protect bit */
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun struct ltq_mm {
30*4882a593Smuzhiyun 	struct of_mm_gpio_chip mmchip;
31*4882a593Smuzhiyun 	u16 shadow;	/* shadow the latches state */
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun /**
35*4882a593Smuzhiyun  * ltq_mm_apply() - write the shadow value to the ebu address.
36*4882a593Smuzhiyun  * @chip:     Pointer to our private data structure.
37*4882a593Smuzhiyun  *
38*4882a593Smuzhiyun  * Write the shadow value to the EBU to set the gpios. We need to set the
39*4882a593Smuzhiyun  * global EBU lock to make sure that PCI/MTD don't break.
40*4882a593Smuzhiyun  */
ltq_mm_apply(struct ltq_mm * chip)41*4882a593Smuzhiyun static void ltq_mm_apply(struct ltq_mm *chip)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun 	unsigned long flags;
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun 	spin_lock_irqsave(&ebu_lock, flags);
46*4882a593Smuzhiyun 	ltq_ebu_w32(LTQ_EBU_BUSCON, LTQ_EBU_BUSCON1);
47*4882a593Smuzhiyun 	__raw_writew(chip->shadow, chip->mmchip.regs);
48*4882a593Smuzhiyun 	ltq_ebu_w32(LTQ_EBU_BUSCON | LTQ_EBU_WP, LTQ_EBU_BUSCON1);
49*4882a593Smuzhiyun 	spin_unlock_irqrestore(&ebu_lock, flags);
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun /**
53*4882a593Smuzhiyun  * ltq_mm_set() - gpio_chip->set - set gpios.
54*4882a593Smuzhiyun  * @gc:     Pointer to gpio_chip device structure.
55*4882a593Smuzhiyun  * @gpio:   GPIO signal number.
56*4882a593Smuzhiyun  * @val:    Value to be written to specified signal.
57*4882a593Smuzhiyun  *
58*4882a593Smuzhiyun  * Set the shadow value and call ltq_mm_apply.
59*4882a593Smuzhiyun  */
ltq_mm_set(struct gpio_chip * gc,unsigned offset,int value)60*4882a593Smuzhiyun static void ltq_mm_set(struct gpio_chip *gc, unsigned offset, int value)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun 	struct ltq_mm *chip = gpiochip_get_data(gc);
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun 	if (value)
65*4882a593Smuzhiyun 		chip->shadow |= (1 << offset);
66*4882a593Smuzhiyun 	else
67*4882a593Smuzhiyun 		chip->shadow &= ~(1 << offset);
68*4882a593Smuzhiyun 	ltq_mm_apply(chip);
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun /**
72*4882a593Smuzhiyun  * ltq_mm_dir_out() - gpio_chip->dir_out - set gpio direction.
73*4882a593Smuzhiyun  * @gc:     Pointer to gpio_chip device structure.
74*4882a593Smuzhiyun  * @gpio:   GPIO signal number.
75*4882a593Smuzhiyun  * @val:    Value to be written to specified signal.
76*4882a593Smuzhiyun  *
77*4882a593Smuzhiyun  * Same as ltq_mm_set, always returns 0.
78*4882a593Smuzhiyun  */
ltq_mm_dir_out(struct gpio_chip * gc,unsigned offset,int value)79*4882a593Smuzhiyun static int ltq_mm_dir_out(struct gpio_chip *gc, unsigned offset, int value)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun 	ltq_mm_set(gc, offset, value);
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 	return 0;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun /**
87*4882a593Smuzhiyun  * ltq_mm_save_regs() - Set initial values of GPIO pins
88*4882a593Smuzhiyun  * @mm_gc: pointer to memory mapped GPIO chip structure
89*4882a593Smuzhiyun  */
ltq_mm_save_regs(struct of_mm_gpio_chip * mm_gc)90*4882a593Smuzhiyun static void ltq_mm_save_regs(struct of_mm_gpio_chip *mm_gc)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun 	struct ltq_mm *chip =
93*4882a593Smuzhiyun 		container_of(mm_gc, struct ltq_mm, mmchip);
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun 	/* tell the ebu controller which memory address we will be using */
96*4882a593Smuzhiyun 	ltq_ebu_w32(CPHYSADDR(chip->mmchip.regs) | 0x1, LTQ_EBU_ADDRSEL1);
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	ltq_mm_apply(chip);
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun 
ltq_mm_probe(struct platform_device * pdev)101*4882a593Smuzhiyun static int ltq_mm_probe(struct platform_device *pdev)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun 	struct ltq_mm *chip;
104*4882a593Smuzhiyun 	u32 shadow;
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
107*4882a593Smuzhiyun 	if (!chip)
108*4882a593Smuzhiyun 		return -ENOMEM;
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	platform_set_drvdata(pdev, chip);
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	chip->mmchip.gc.ngpio = 16;
113*4882a593Smuzhiyun 	chip->mmchip.gc.direction_output = ltq_mm_dir_out;
114*4882a593Smuzhiyun 	chip->mmchip.gc.set = ltq_mm_set;
115*4882a593Smuzhiyun 	chip->mmchip.save_regs = ltq_mm_save_regs;
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	/* store the shadow value if one was passed by the devicetree */
118*4882a593Smuzhiyun 	if (!of_property_read_u32(pdev->dev.of_node, "lantiq,shadow", &shadow))
119*4882a593Smuzhiyun 		chip->shadow = shadow;
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 	return of_mm_gpiochip_add_data(pdev->dev.of_node, &chip->mmchip, chip);
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun 
ltq_mm_remove(struct platform_device * pdev)124*4882a593Smuzhiyun static int ltq_mm_remove(struct platform_device *pdev)
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun 	struct ltq_mm *chip = platform_get_drvdata(pdev);
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	of_mm_gpiochip_remove(&chip->mmchip);
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	return 0;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun static const struct of_device_id ltq_mm_match[] = {
134*4882a593Smuzhiyun 	{ .compatible = "lantiq,gpio-mm" },
135*4882a593Smuzhiyun 	{},
136*4882a593Smuzhiyun };
137*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, ltq_mm_match);
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun static struct platform_driver ltq_mm_driver = {
140*4882a593Smuzhiyun 	.probe = ltq_mm_probe,
141*4882a593Smuzhiyun 	.remove = ltq_mm_remove,
142*4882a593Smuzhiyun 	.driver = {
143*4882a593Smuzhiyun 		.name = "gpio-mm-ltq",
144*4882a593Smuzhiyun 		.of_match_table = ltq_mm_match,
145*4882a593Smuzhiyun 	},
146*4882a593Smuzhiyun };
147*4882a593Smuzhiyun 
ltq_mm_init(void)148*4882a593Smuzhiyun static int __init ltq_mm_init(void)
149*4882a593Smuzhiyun {
150*4882a593Smuzhiyun 	return platform_driver_register(&ltq_mm_driver);
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun subsys_initcall(ltq_mm_init);
154*4882a593Smuzhiyun 
ltq_mm_exit(void)155*4882a593Smuzhiyun static void __exit ltq_mm_exit(void)
156*4882a593Smuzhiyun {
157*4882a593Smuzhiyun 	platform_driver_unregister(&ltq_mm_driver);
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun module_exit(ltq_mm_exit);
160