1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun
3*4882a593Smuzhiyun #include <linux/acpi.h>
4*4882a593Smuzhiyun #include <linux/bitops.h>
5*4882a593Smuzhiyun #include <linux/device.h>
6*4882a593Smuzhiyun #include <linux/gpio/driver.h>
7*4882a593Smuzhiyun #include <linux/io.h>
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/platform_device.h>
11*4882a593Smuzhiyun #include <linux/pm.h>
12*4882a593Smuzhiyun #include <linux/resource.h>
13*4882a593Smuzhiyun #include <linux/types.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun /* Number of pins on BlueField */
16*4882a593Smuzhiyun #define MLXBF_GPIO_NR 54
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /* Pad Electrical Controls. */
19*4882a593Smuzhiyun #define MLXBF_GPIO_PAD_CONTROL_FIRST_WORD 0x0700
20*4882a593Smuzhiyun #define MLXBF_GPIO_PAD_CONTROL_1_FIRST_WORD 0x0708
21*4882a593Smuzhiyun #define MLXBF_GPIO_PAD_CONTROL_2_FIRST_WORD 0x0710
22*4882a593Smuzhiyun #define MLXBF_GPIO_PAD_CONTROL_3_FIRST_WORD 0x0718
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define MLXBF_GPIO_PIN_DIR_I 0x1040
25*4882a593Smuzhiyun #define MLXBF_GPIO_PIN_DIR_O 0x1048
26*4882a593Smuzhiyun #define MLXBF_GPIO_PIN_STATE 0x1000
27*4882a593Smuzhiyun #define MLXBF_GPIO_SCRATCHPAD 0x20
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #ifdef CONFIG_PM
30*4882a593Smuzhiyun struct mlxbf_gpio_context_save_regs {
31*4882a593Smuzhiyun u64 scratchpad;
32*4882a593Smuzhiyun u64 pad_control[MLXBF_GPIO_NR];
33*4882a593Smuzhiyun u64 pin_dir_i;
34*4882a593Smuzhiyun u64 pin_dir_o;
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun #endif
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /* Device state structure. */
39*4882a593Smuzhiyun struct mlxbf_gpio_state {
40*4882a593Smuzhiyun struct gpio_chip gc;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /* Memory Address */
43*4882a593Smuzhiyun void __iomem *base;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun #ifdef CONFIG_PM
46*4882a593Smuzhiyun struct mlxbf_gpio_context_save_regs csave_regs;
47*4882a593Smuzhiyun #endif
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun
mlxbf_gpio_probe(struct platform_device * pdev)50*4882a593Smuzhiyun static int mlxbf_gpio_probe(struct platform_device *pdev)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun struct mlxbf_gpio_state *gs;
53*4882a593Smuzhiyun struct device *dev = &pdev->dev;
54*4882a593Smuzhiyun struct gpio_chip *gc;
55*4882a593Smuzhiyun int ret;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun gs = devm_kzalloc(&pdev->dev, sizeof(*gs), GFP_KERNEL);
58*4882a593Smuzhiyun if (!gs)
59*4882a593Smuzhiyun return -ENOMEM;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun gs->base = devm_platform_ioremap_resource(pdev, 0);
62*4882a593Smuzhiyun if (IS_ERR(gs->base))
63*4882a593Smuzhiyun return PTR_ERR(gs->base);
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun gc = &gs->gc;
66*4882a593Smuzhiyun ret = bgpio_init(gc, dev, 8,
67*4882a593Smuzhiyun gs->base + MLXBF_GPIO_PIN_STATE,
68*4882a593Smuzhiyun NULL,
69*4882a593Smuzhiyun NULL,
70*4882a593Smuzhiyun gs->base + MLXBF_GPIO_PIN_DIR_O,
71*4882a593Smuzhiyun gs->base + MLXBF_GPIO_PIN_DIR_I,
72*4882a593Smuzhiyun 0);
73*4882a593Smuzhiyun if (ret)
74*4882a593Smuzhiyun return -ENODEV;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun gc->owner = THIS_MODULE;
77*4882a593Smuzhiyun gc->ngpio = MLXBF_GPIO_NR;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun ret = devm_gpiochip_add_data(dev, &gs->gc, gs);
80*4882a593Smuzhiyun if (ret) {
81*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed adding memory mapped gpiochip\n");
82*4882a593Smuzhiyun return ret;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun platform_set_drvdata(pdev, gs);
86*4882a593Smuzhiyun dev_info(&pdev->dev, "registered Mellanox BlueField GPIO");
87*4882a593Smuzhiyun return 0;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun #ifdef CONFIG_PM
mlxbf_gpio_suspend(struct platform_device * pdev,pm_message_t state)91*4882a593Smuzhiyun static int mlxbf_gpio_suspend(struct platform_device *pdev, pm_message_t state)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun struct mlxbf_gpio_state *gs = platform_get_drvdata(pdev);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun gs->csave_regs.scratchpad = readq(gs->base + MLXBF_GPIO_SCRATCHPAD);
96*4882a593Smuzhiyun gs->csave_regs.pad_control[0] =
97*4882a593Smuzhiyun readq(gs->base + MLXBF_GPIO_PAD_CONTROL_FIRST_WORD);
98*4882a593Smuzhiyun gs->csave_regs.pad_control[1] =
99*4882a593Smuzhiyun readq(gs->base + MLXBF_GPIO_PAD_CONTROL_1_FIRST_WORD);
100*4882a593Smuzhiyun gs->csave_regs.pad_control[2] =
101*4882a593Smuzhiyun readq(gs->base + MLXBF_GPIO_PAD_CONTROL_2_FIRST_WORD);
102*4882a593Smuzhiyun gs->csave_regs.pad_control[3] =
103*4882a593Smuzhiyun readq(gs->base + MLXBF_GPIO_PAD_CONTROL_3_FIRST_WORD);
104*4882a593Smuzhiyun gs->csave_regs.pin_dir_i = readq(gs->base + MLXBF_GPIO_PIN_DIR_I);
105*4882a593Smuzhiyun gs->csave_regs.pin_dir_o = readq(gs->base + MLXBF_GPIO_PIN_DIR_O);
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun return 0;
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun
mlxbf_gpio_resume(struct platform_device * pdev)110*4882a593Smuzhiyun static int mlxbf_gpio_resume(struct platform_device *pdev)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun struct mlxbf_gpio_state *gs = platform_get_drvdata(pdev);
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun writeq(gs->csave_regs.scratchpad, gs->base + MLXBF_GPIO_SCRATCHPAD);
115*4882a593Smuzhiyun writeq(gs->csave_regs.pad_control[0],
116*4882a593Smuzhiyun gs->base + MLXBF_GPIO_PAD_CONTROL_FIRST_WORD);
117*4882a593Smuzhiyun writeq(gs->csave_regs.pad_control[1],
118*4882a593Smuzhiyun gs->base + MLXBF_GPIO_PAD_CONTROL_1_FIRST_WORD);
119*4882a593Smuzhiyun writeq(gs->csave_regs.pad_control[2],
120*4882a593Smuzhiyun gs->base + MLXBF_GPIO_PAD_CONTROL_2_FIRST_WORD);
121*4882a593Smuzhiyun writeq(gs->csave_regs.pad_control[3],
122*4882a593Smuzhiyun gs->base + MLXBF_GPIO_PAD_CONTROL_3_FIRST_WORD);
123*4882a593Smuzhiyun writeq(gs->csave_regs.pin_dir_i, gs->base + MLXBF_GPIO_PIN_DIR_I);
124*4882a593Smuzhiyun writeq(gs->csave_regs.pin_dir_o, gs->base + MLXBF_GPIO_PIN_DIR_O);
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun return 0;
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun #endif
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun static const struct acpi_device_id __maybe_unused mlxbf_gpio_acpi_match[] = {
131*4882a593Smuzhiyun { "MLNXBF02", 0 },
132*4882a593Smuzhiyun {}
133*4882a593Smuzhiyun };
134*4882a593Smuzhiyun MODULE_DEVICE_TABLE(acpi, mlxbf_gpio_acpi_match);
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun static struct platform_driver mlxbf_gpio_driver = {
137*4882a593Smuzhiyun .driver = {
138*4882a593Smuzhiyun .name = "mlxbf_gpio",
139*4882a593Smuzhiyun .acpi_match_table = ACPI_PTR(mlxbf_gpio_acpi_match),
140*4882a593Smuzhiyun },
141*4882a593Smuzhiyun .probe = mlxbf_gpio_probe,
142*4882a593Smuzhiyun #ifdef CONFIG_PM
143*4882a593Smuzhiyun .suspend = mlxbf_gpio_suspend,
144*4882a593Smuzhiyun .resume = mlxbf_gpio_resume,
145*4882a593Smuzhiyun #endif
146*4882a593Smuzhiyun };
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun module_platform_driver(mlxbf_gpio_driver);
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun MODULE_DESCRIPTION("Mellanox BlueField GPIO Driver");
151*4882a593Smuzhiyun MODULE_AUTHOR("Mellanox Technologies");
152*4882a593Smuzhiyun MODULE_LICENSE("GPL");
153