xref: /OK3568_Linux_fs/kernel/drivers/gpio/gpio-max77650.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Copyright (C) 2018 BayLibre SAS
4*4882a593Smuzhiyun // Author: Bartosz Golaszewski <bgolaszewski@baylibre.com>
5*4882a593Smuzhiyun //
6*4882a593Smuzhiyun // GPIO driver for MAXIM 77650/77651 charger/power-supply.
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/gpio/driver.h>
9*4882a593Smuzhiyun #include <linux/i2c.h>
10*4882a593Smuzhiyun #include <linux/mfd/max77650.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/platform_device.h>
13*4882a593Smuzhiyun #include <linux/regmap.h>
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #define MAX77650_GPIO_DIR_MASK		BIT(0)
16*4882a593Smuzhiyun #define MAX77650_GPIO_INVAL_MASK	BIT(1)
17*4882a593Smuzhiyun #define MAX77650_GPIO_DRV_MASK		BIT(2)
18*4882a593Smuzhiyun #define MAX77650_GPIO_OUTVAL_MASK	BIT(3)
19*4882a593Smuzhiyun #define MAX77650_GPIO_DEBOUNCE_MASK	BIT(4)
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #define MAX77650_GPIO_DIR_OUT		0x00
22*4882a593Smuzhiyun #define MAX77650_GPIO_DIR_IN		BIT(0)
23*4882a593Smuzhiyun #define MAX77650_GPIO_OUT_LOW		0x00
24*4882a593Smuzhiyun #define MAX77650_GPIO_OUT_HIGH		BIT(3)
25*4882a593Smuzhiyun #define MAX77650_GPIO_DRV_OPEN_DRAIN	0x00
26*4882a593Smuzhiyun #define MAX77650_GPIO_DRV_PUSH_PULL	BIT(2)
27*4882a593Smuzhiyun #define MAX77650_GPIO_DEBOUNCE		BIT(4)
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun #define MAX77650_GPIO_DIR_BITS(_reg) \
30*4882a593Smuzhiyun 		((_reg) & MAX77650_GPIO_DIR_MASK)
31*4882a593Smuzhiyun #define MAX77650_GPIO_INVAL_BITS(_reg) \
32*4882a593Smuzhiyun 		(((_reg) & MAX77650_GPIO_INVAL_MASK) >> 1)
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun struct max77650_gpio_chip {
35*4882a593Smuzhiyun 	struct regmap *map;
36*4882a593Smuzhiyun 	struct gpio_chip gc;
37*4882a593Smuzhiyun 	int irq;
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun 
max77650_gpio_direction_input(struct gpio_chip * gc,unsigned int offset)40*4882a593Smuzhiyun static int max77650_gpio_direction_input(struct gpio_chip *gc,
41*4882a593Smuzhiyun 					 unsigned int offset)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun 	struct max77650_gpio_chip *chip = gpiochip_get_data(gc);
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun 	return regmap_update_bits(chip->map,
46*4882a593Smuzhiyun 				  MAX77650_REG_CNFG_GPIO,
47*4882a593Smuzhiyun 				  MAX77650_GPIO_DIR_MASK,
48*4882a593Smuzhiyun 				  MAX77650_GPIO_DIR_IN);
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun 
max77650_gpio_direction_output(struct gpio_chip * gc,unsigned int offset,int value)51*4882a593Smuzhiyun static int max77650_gpio_direction_output(struct gpio_chip *gc,
52*4882a593Smuzhiyun 					  unsigned int offset, int value)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun 	struct max77650_gpio_chip *chip = gpiochip_get_data(gc);
55*4882a593Smuzhiyun 	int mask, regval;
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 	mask = MAX77650_GPIO_DIR_MASK | MAX77650_GPIO_OUTVAL_MASK;
58*4882a593Smuzhiyun 	regval = value ? MAX77650_GPIO_OUT_HIGH : MAX77650_GPIO_OUT_LOW;
59*4882a593Smuzhiyun 	regval |= MAX77650_GPIO_DIR_OUT;
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun 	return regmap_update_bits(chip->map,
62*4882a593Smuzhiyun 				  MAX77650_REG_CNFG_GPIO, mask, regval);
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun 
max77650_gpio_set_value(struct gpio_chip * gc,unsigned int offset,int value)65*4882a593Smuzhiyun static void max77650_gpio_set_value(struct gpio_chip *gc,
66*4882a593Smuzhiyun 				    unsigned int offset, int value)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun 	struct max77650_gpio_chip *chip = gpiochip_get_data(gc);
69*4882a593Smuzhiyun 	int rv, regval;
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun 	regval = value ? MAX77650_GPIO_OUT_HIGH : MAX77650_GPIO_OUT_LOW;
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	rv = regmap_update_bits(chip->map, MAX77650_REG_CNFG_GPIO,
74*4882a593Smuzhiyun 				MAX77650_GPIO_OUTVAL_MASK, regval);
75*4882a593Smuzhiyun 	if (rv)
76*4882a593Smuzhiyun 		dev_err(gc->parent, "cannot set GPIO value: %d\n", rv);
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun 
max77650_gpio_get_value(struct gpio_chip * gc,unsigned int offset)79*4882a593Smuzhiyun static int max77650_gpio_get_value(struct gpio_chip *gc,
80*4882a593Smuzhiyun 				   unsigned int offset)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun 	struct max77650_gpio_chip *chip = gpiochip_get_data(gc);
83*4882a593Smuzhiyun 	unsigned int val;
84*4882a593Smuzhiyun 	int rv;
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 	rv = regmap_read(chip->map, MAX77650_REG_CNFG_GPIO, &val);
87*4882a593Smuzhiyun 	if (rv)
88*4882a593Smuzhiyun 		return rv;
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	return MAX77650_GPIO_INVAL_BITS(val);
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun 
max77650_gpio_get_direction(struct gpio_chip * gc,unsigned int offset)93*4882a593Smuzhiyun static int max77650_gpio_get_direction(struct gpio_chip *gc,
94*4882a593Smuzhiyun 				       unsigned int offset)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun 	struct max77650_gpio_chip *chip = gpiochip_get_data(gc);
97*4882a593Smuzhiyun 	unsigned int val;
98*4882a593Smuzhiyun 	int rv;
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	rv = regmap_read(chip->map, MAX77650_REG_CNFG_GPIO, &val);
101*4882a593Smuzhiyun 	if (rv)
102*4882a593Smuzhiyun 		return rv;
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun 	return MAX77650_GPIO_DIR_BITS(val);
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun 
max77650_gpio_set_config(struct gpio_chip * gc,unsigned int offset,unsigned long cfg)107*4882a593Smuzhiyun static int max77650_gpio_set_config(struct gpio_chip *gc,
108*4882a593Smuzhiyun 				    unsigned int offset, unsigned long cfg)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun 	struct max77650_gpio_chip *chip = gpiochip_get_data(gc);
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	switch (pinconf_to_config_param(cfg)) {
113*4882a593Smuzhiyun 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
114*4882a593Smuzhiyun 		return regmap_update_bits(chip->map,
115*4882a593Smuzhiyun 					  MAX77650_REG_CNFG_GPIO,
116*4882a593Smuzhiyun 					  MAX77650_GPIO_DRV_MASK,
117*4882a593Smuzhiyun 					  MAX77650_GPIO_DRV_OPEN_DRAIN);
118*4882a593Smuzhiyun 	case PIN_CONFIG_DRIVE_PUSH_PULL:
119*4882a593Smuzhiyun 		return regmap_update_bits(chip->map,
120*4882a593Smuzhiyun 					  MAX77650_REG_CNFG_GPIO,
121*4882a593Smuzhiyun 					  MAX77650_GPIO_DRV_MASK,
122*4882a593Smuzhiyun 					  MAX77650_GPIO_DRV_PUSH_PULL);
123*4882a593Smuzhiyun 	case PIN_CONFIG_INPUT_DEBOUNCE:
124*4882a593Smuzhiyun 		return regmap_update_bits(chip->map,
125*4882a593Smuzhiyun 					  MAX77650_REG_CNFG_GPIO,
126*4882a593Smuzhiyun 					  MAX77650_GPIO_DEBOUNCE_MASK,
127*4882a593Smuzhiyun 					  MAX77650_GPIO_DEBOUNCE);
128*4882a593Smuzhiyun 	default:
129*4882a593Smuzhiyun 		return -ENOTSUPP;
130*4882a593Smuzhiyun 	}
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun 
max77650_gpio_to_irq(struct gpio_chip * gc,unsigned int offset)133*4882a593Smuzhiyun static int max77650_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun 	struct max77650_gpio_chip *chip = gpiochip_get_data(gc);
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	return chip->irq;
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun 
max77650_gpio_probe(struct platform_device * pdev)140*4882a593Smuzhiyun static int max77650_gpio_probe(struct platform_device *pdev)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun 	struct max77650_gpio_chip *chip;
143*4882a593Smuzhiyun 	struct device *dev, *parent;
144*4882a593Smuzhiyun 	struct i2c_client *i2c;
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 	dev = &pdev->dev;
147*4882a593Smuzhiyun 	parent = dev->parent;
148*4882a593Smuzhiyun 	i2c = to_i2c_client(parent);
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
151*4882a593Smuzhiyun 	if (!chip)
152*4882a593Smuzhiyun 		return -ENOMEM;
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 	chip->map = dev_get_regmap(parent, NULL);
155*4882a593Smuzhiyun 	if (!chip->map)
156*4882a593Smuzhiyun 		return -ENODEV;
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 	chip->irq = platform_get_irq_byname(pdev, "GPI");
159*4882a593Smuzhiyun 	if (chip->irq < 0)
160*4882a593Smuzhiyun 		return chip->irq;
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 	chip->gc.base = -1;
163*4882a593Smuzhiyun 	chip->gc.ngpio = 1;
164*4882a593Smuzhiyun 	chip->gc.label = i2c->name;
165*4882a593Smuzhiyun 	chip->gc.parent = dev;
166*4882a593Smuzhiyun 	chip->gc.owner = THIS_MODULE;
167*4882a593Smuzhiyun 	chip->gc.can_sleep = true;
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun 	chip->gc.direction_input = max77650_gpio_direction_input;
170*4882a593Smuzhiyun 	chip->gc.direction_output = max77650_gpio_direction_output;
171*4882a593Smuzhiyun 	chip->gc.set = max77650_gpio_set_value;
172*4882a593Smuzhiyun 	chip->gc.get = max77650_gpio_get_value;
173*4882a593Smuzhiyun 	chip->gc.get_direction = max77650_gpio_get_direction;
174*4882a593Smuzhiyun 	chip->gc.set_config = max77650_gpio_set_config;
175*4882a593Smuzhiyun 	chip->gc.to_irq = max77650_gpio_to_irq;
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	return devm_gpiochip_add_data(dev, &chip->gc, chip);
178*4882a593Smuzhiyun }
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun static struct platform_driver max77650_gpio_driver = {
181*4882a593Smuzhiyun 	.driver = {
182*4882a593Smuzhiyun 		.name = "max77650-gpio",
183*4882a593Smuzhiyun 	},
184*4882a593Smuzhiyun 	.probe = max77650_gpio_probe,
185*4882a593Smuzhiyun };
186*4882a593Smuzhiyun module_platform_driver(max77650_gpio_driver);
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun MODULE_DESCRIPTION("MAXIM 77650/77651 GPIO driver");
189*4882a593Smuzhiyun MODULE_AUTHOR("Bartosz Golaszewski <bgolaszewski@baylibre.com>");
190*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
191*4882a593Smuzhiyun MODULE_ALIAS("platform:max77650-gpio");
192