1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
3*4882a593Smuzhiyun * Keerthy <j-keerthy@ti.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or
6*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License version 2 as
7*4882a593Smuzhiyun * published by the Free Software Foundation.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * This program is distributed "as is" WITHOUT ANY WARRANTY of any
10*4882a593Smuzhiyun * kind, whether expressed or implied; without even the implied warranty
11*4882a593Smuzhiyun * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12*4882a593Smuzhiyun * GNU General Public License version 2 for more details.
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * Based on the LP873X driver
15*4882a593Smuzhiyun */
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <linux/gpio/driver.h>
18*4882a593Smuzhiyun #include <linux/module.h>
19*4882a593Smuzhiyun #include <linux/platform_device.h>
20*4882a593Smuzhiyun #include <linux/regmap.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #include <linux/mfd/lp87565.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun struct lp87565_gpio {
25*4882a593Smuzhiyun struct gpio_chip chip;
26*4882a593Smuzhiyun struct regmap *map;
27*4882a593Smuzhiyun };
28*4882a593Smuzhiyun
lp87565_gpio_get(struct gpio_chip * chip,unsigned int offset)29*4882a593Smuzhiyun static int lp87565_gpio_get(struct gpio_chip *chip, unsigned int offset)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun struct lp87565_gpio *gpio = gpiochip_get_data(chip);
32*4882a593Smuzhiyun int ret, val;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun ret = regmap_read(gpio->map, LP87565_REG_GPIO_IN, &val);
35*4882a593Smuzhiyun if (ret < 0)
36*4882a593Smuzhiyun return ret;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun return !!(val & BIT(offset));
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
lp87565_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)41*4882a593Smuzhiyun static void lp87565_gpio_set(struct gpio_chip *chip, unsigned int offset,
42*4882a593Smuzhiyun int value)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun struct lp87565_gpio *gpio = gpiochip_get_data(chip);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun regmap_update_bits(gpio->map, LP87565_REG_GPIO_OUT,
47*4882a593Smuzhiyun BIT(offset), value ? BIT(offset) : 0);
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
lp87565_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)50*4882a593Smuzhiyun static int lp87565_gpio_get_direction(struct gpio_chip *chip,
51*4882a593Smuzhiyun unsigned int offset)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun struct lp87565_gpio *gpio = gpiochip_get_data(chip);
54*4882a593Smuzhiyun int ret, val;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun ret = regmap_read(gpio->map, LP87565_REG_GPIO_CONFIG, &val);
57*4882a593Smuzhiyun if (ret < 0)
58*4882a593Smuzhiyun return ret;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun if (val & BIT(offset))
61*4882a593Smuzhiyun return GPIO_LINE_DIRECTION_OUT;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun return GPIO_LINE_DIRECTION_IN;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
lp87565_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)66*4882a593Smuzhiyun static int lp87565_gpio_direction_input(struct gpio_chip *chip,
67*4882a593Smuzhiyun unsigned int offset)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun struct lp87565_gpio *gpio = gpiochip_get_data(chip);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun return regmap_update_bits(gpio->map,
72*4882a593Smuzhiyun LP87565_REG_GPIO_CONFIG,
73*4882a593Smuzhiyun BIT(offset), 0);
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
lp87565_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)76*4882a593Smuzhiyun static int lp87565_gpio_direction_output(struct gpio_chip *chip,
77*4882a593Smuzhiyun unsigned int offset, int value)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun struct lp87565_gpio *gpio = gpiochip_get_data(chip);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun lp87565_gpio_set(chip, offset, value);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun return regmap_update_bits(gpio->map,
84*4882a593Smuzhiyun LP87565_REG_GPIO_CONFIG,
85*4882a593Smuzhiyun BIT(offset), BIT(offset));
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
lp87565_gpio_request(struct gpio_chip * gc,unsigned int offset)88*4882a593Smuzhiyun static int lp87565_gpio_request(struct gpio_chip *gc, unsigned int offset)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun struct lp87565_gpio *gpio = gpiochip_get_data(gc);
91*4882a593Smuzhiyun int ret;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun switch (offset) {
94*4882a593Smuzhiyun case 0:
95*4882a593Smuzhiyun case 1:
96*4882a593Smuzhiyun case 2:
97*4882a593Smuzhiyun /*
98*4882a593Smuzhiyun * MUX can program the pin to be in EN1/2/3 pin mode
99*4882a593Smuzhiyun * Or GPIO1/2/3 mode.
100*4882a593Smuzhiyun * Setup the GPIO*_SEL MUX to GPIO mode
101*4882a593Smuzhiyun */
102*4882a593Smuzhiyun ret = regmap_update_bits(gpio->map,
103*4882a593Smuzhiyun LP87565_REG_PIN_FUNCTION,
104*4882a593Smuzhiyun BIT(offset), BIT(offset));
105*4882a593Smuzhiyun if (ret)
106*4882a593Smuzhiyun return ret;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun break;
109*4882a593Smuzhiyun default:
110*4882a593Smuzhiyun return -EINVAL;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun return 0;
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun
lp87565_gpio_set_config(struct gpio_chip * gc,unsigned int offset,unsigned long config)116*4882a593Smuzhiyun static int lp87565_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
117*4882a593Smuzhiyun unsigned long config)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun struct lp87565_gpio *gpio = gpiochip_get_data(gc);
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun switch (pinconf_to_config_param(config)) {
122*4882a593Smuzhiyun case PIN_CONFIG_DRIVE_OPEN_DRAIN:
123*4882a593Smuzhiyun return regmap_update_bits(gpio->map,
124*4882a593Smuzhiyun LP87565_REG_GPIO_CONFIG,
125*4882a593Smuzhiyun BIT(offset +
126*4882a593Smuzhiyun __ffs(LP87565_GOIO1_OD)),
127*4882a593Smuzhiyun BIT(offset +
128*4882a593Smuzhiyun __ffs(LP87565_GOIO1_OD)));
129*4882a593Smuzhiyun case PIN_CONFIG_DRIVE_PUSH_PULL:
130*4882a593Smuzhiyun return regmap_update_bits(gpio->map,
131*4882a593Smuzhiyun LP87565_REG_GPIO_CONFIG,
132*4882a593Smuzhiyun BIT(offset +
133*4882a593Smuzhiyun __ffs(LP87565_GOIO1_OD)), 0);
134*4882a593Smuzhiyun default:
135*4882a593Smuzhiyun return -ENOTSUPP;
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun static const struct gpio_chip template_chip = {
140*4882a593Smuzhiyun .label = "lp87565-gpio",
141*4882a593Smuzhiyun .owner = THIS_MODULE,
142*4882a593Smuzhiyun .request = lp87565_gpio_request,
143*4882a593Smuzhiyun .get_direction = lp87565_gpio_get_direction,
144*4882a593Smuzhiyun .direction_input = lp87565_gpio_direction_input,
145*4882a593Smuzhiyun .direction_output = lp87565_gpio_direction_output,
146*4882a593Smuzhiyun .get = lp87565_gpio_get,
147*4882a593Smuzhiyun .set = lp87565_gpio_set,
148*4882a593Smuzhiyun .set_config = lp87565_gpio_set_config,
149*4882a593Smuzhiyun .base = -1,
150*4882a593Smuzhiyun .ngpio = 3,
151*4882a593Smuzhiyun .can_sleep = true,
152*4882a593Smuzhiyun };
153*4882a593Smuzhiyun
lp87565_gpio_probe(struct platform_device * pdev)154*4882a593Smuzhiyun static int lp87565_gpio_probe(struct platform_device *pdev)
155*4882a593Smuzhiyun {
156*4882a593Smuzhiyun struct lp87565_gpio *gpio;
157*4882a593Smuzhiyun struct lp87565 *lp87565;
158*4882a593Smuzhiyun int ret;
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
161*4882a593Smuzhiyun if (!gpio)
162*4882a593Smuzhiyun return -ENOMEM;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun lp87565 = dev_get_drvdata(pdev->dev.parent);
165*4882a593Smuzhiyun gpio->chip = template_chip;
166*4882a593Smuzhiyun gpio->chip.parent = lp87565->dev;
167*4882a593Smuzhiyun gpio->map = lp87565->regmap;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun ret = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
170*4882a593Smuzhiyun if (ret < 0) {
171*4882a593Smuzhiyun dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret);
172*4882a593Smuzhiyun return ret;
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun return 0;
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun static const struct platform_device_id lp87565_gpio_id_table[] = {
179*4882a593Smuzhiyun { "lp87565-q1-gpio", },
180*4882a593Smuzhiyun { /* sentinel */ }
181*4882a593Smuzhiyun };
182*4882a593Smuzhiyun MODULE_DEVICE_TABLE(platform, lp87565_gpio_id_table);
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun static struct platform_driver lp87565_gpio_driver = {
185*4882a593Smuzhiyun .driver = {
186*4882a593Smuzhiyun .name = "lp87565-gpio",
187*4882a593Smuzhiyun },
188*4882a593Smuzhiyun .probe = lp87565_gpio_probe,
189*4882a593Smuzhiyun .id_table = lp87565_gpio_id_table,
190*4882a593Smuzhiyun };
191*4882a593Smuzhiyun module_platform_driver(lp87565_gpio_driver);
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun MODULE_AUTHOR("Keerthy <j-keerthy@ti.com>");
194*4882a593Smuzhiyun MODULE_DESCRIPTION("LP87565 GPIO driver");
195*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
196