xref: /OK3568_Linux_fs/kernel/drivers/gpio/gpio-lp3943.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * TI/National Semiconductor LP3943 GPIO driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright 2013 Texas Instruments
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Author: Milo Kim <milo.kim@ti.com>
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/bitops.h>
11*4882a593Smuzhiyun #include <linux/err.h>
12*4882a593Smuzhiyun #include <linux/gpio/driver.h>
13*4882a593Smuzhiyun #include <linux/i2c.h>
14*4882a593Smuzhiyun #include <linux/mfd/lp3943.h>
15*4882a593Smuzhiyun #include <linux/module.h>
16*4882a593Smuzhiyun #include <linux/platform_device.h>
17*4882a593Smuzhiyun #include <linux/slab.h>
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun enum lp3943_gpios {
20*4882a593Smuzhiyun 	LP3943_GPIO1,
21*4882a593Smuzhiyun 	LP3943_GPIO2,
22*4882a593Smuzhiyun 	LP3943_GPIO3,
23*4882a593Smuzhiyun 	LP3943_GPIO4,
24*4882a593Smuzhiyun 	LP3943_GPIO5,
25*4882a593Smuzhiyun 	LP3943_GPIO6,
26*4882a593Smuzhiyun 	LP3943_GPIO7,
27*4882a593Smuzhiyun 	LP3943_GPIO8,
28*4882a593Smuzhiyun 	LP3943_GPIO9,
29*4882a593Smuzhiyun 	LP3943_GPIO10,
30*4882a593Smuzhiyun 	LP3943_GPIO11,
31*4882a593Smuzhiyun 	LP3943_GPIO12,
32*4882a593Smuzhiyun 	LP3943_GPIO13,
33*4882a593Smuzhiyun 	LP3943_GPIO14,
34*4882a593Smuzhiyun 	LP3943_GPIO15,
35*4882a593Smuzhiyun 	LP3943_GPIO16,
36*4882a593Smuzhiyun 	LP3943_MAX_GPIO,
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun struct lp3943_gpio {
40*4882a593Smuzhiyun 	struct gpio_chip chip;
41*4882a593Smuzhiyun 	struct lp3943 *lp3943;
42*4882a593Smuzhiyun 	u16 input_mask;		/* 1 = GPIO is input direction, 0 = output */
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun 
lp3943_gpio_request(struct gpio_chip * chip,unsigned offset)45*4882a593Smuzhiyun static int lp3943_gpio_request(struct gpio_chip *chip, unsigned offset)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun 	struct lp3943_gpio *lp3943_gpio = gpiochip_get_data(chip);
48*4882a593Smuzhiyun 	struct lp3943 *lp3943 = lp3943_gpio->lp3943;
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun 	/* Return an error if the pin is already assigned */
51*4882a593Smuzhiyun 	if (test_and_set_bit(offset, &lp3943->pin_used))
52*4882a593Smuzhiyun 		return -EBUSY;
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun 	return 0;
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun 
lp3943_gpio_free(struct gpio_chip * chip,unsigned offset)57*4882a593Smuzhiyun static void lp3943_gpio_free(struct gpio_chip *chip, unsigned offset)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun 	struct lp3943_gpio *lp3943_gpio = gpiochip_get_data(chip);
60*4882a593Smuzhiyun 	struct lp3943 *lp3943 = lp3943_gpio->lp3943;
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 	clear_bit(offset, &lp3943->pin_used);
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun 
lp3943_gpio_set_mode(struct lp3943_gpio * lp3943_gpio,u8 offset,u8 val)65*4882a593Smuzhiyun static int lp3943_gpio_set_mode(struct lp3943_gpio *lp3943_gpio, u8 offset,
66*4882a593Smuzhiyun 				u8 val)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun 	struct lp3943 *lp3943 = lp3943_gpio->lp3943;
69*4882a593Smuzhiyun 	const struct lp3943_reg_cfg *mux = lp3943->mux_cfg;
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun 	return lp3943_update_bits(lp3943, mux[offset].reg, mux[offset].mask,
72*4882a593Smuzhiyun 				  val << mux[offset].shift);
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun 
lp3943_gpio_direction_input(struct gpio_chip * chip,unsigned offset)75*4882a593Smuzhiyun static int lp3943_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun 	struct lp3943_gpio *lp3943_gpio = gpiochip_get_data(chip);
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 	lp3943_gpio->input_mask |= BIT(offset);
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun 	return lp3943_gpio_set_mode(lp3943_gpio, offset, LP3943_GPIO_IN);
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun 
lp3943_get_gpio_in_status(struct lp3943_gpio * lp3943_gpio,struct gpio_chip * chip,unsigned offset)84*4882a593Smuzhiyun static int lp3943_get_gpio_in_status(struct lp3943_gpio *lp3943_gpio,
85*4882a593Smuzhiyun 				     struct gpio_chip *chip, unsigned offset)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun 	u8 addr, read;
88*4882a593Smuzhiyun 	int err;
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	switch (offset) {
91*4882a593Smuzhiyun 	case LP3943_GPIO1 ... LP3943_GPIO8:
92*4882a593Smuzhiyun 		addr = LP3943_REG_GPIO_A;
93*4882a593Smuzhiyun 		break;
94*4882a593Smuzhiyun 	case LP3943_GPIO9 ... LP3943_GPIO16:
95*4882a593Smuzhiyun 		addr = LP3943_REG_GPIO_B;
96*4882a593Smuzhiyun 		offset = offset - 8;
97*4882a593Smuzhiyun 		break;
98*4882a593Smuzhiyun 	default:
99*4882a593Smuzhiyun 		return -EINVAL;
100*4882a593Smuzhiyun 	}
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 	err = lp3943_read_byte(lp3943_gpio->lp3943, addr, &read);
103*4882a593Smuzhiyun 	if (err)
104*4882a593Smuzhiyun 		return err;
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	return !!(read & BIT(offset));
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun 
lp3943_get_gpio_out_status(struct lp3943_gpio * lp3943_gpio,struct gpio_chip * chip,unsigned offset)109*4882a593Smuzhiyun static int lp3943_get_gpio_out_status(struct lp3943_gpio *lp3943_gpio,
110*4882a593Smuzhiyun 				      struct gpio_chip *chip, unsigned offset)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun 	struct lp3943 *lp3943 = lp3943_gpio->lp3943;
113*4882a593Smuzhiyun 	const struct lp3943_reg_cfg *mux = lp3943->mux_cfg;
114*4882a593Smuzhiyun 	u8 read;
115*4882a593Smuzhiyun 	int err;
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	err = lp3943_read_byte(lp3943, mux[offset].reg, &read);
118*4882a593Smuzhiyun 	if (err)
119*4882a593Smuzhiyun 		return err;
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 	read = (read & mux[offset].mask) >> mux[offset].shift;
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	if (read == LP3943_GPIO_OUT_HIGH)
124*4882a593Smuzhiyun 		return 1;
125*4882a593Smuzhiyun 	else if (read == LP3943_GPIO_OUT_LOW)
126*4882a593Smuzhiyun 		return 0;
127*4882a593Smuzhiyun 	else
128*4882a593Smuzhiyun 		return -EINVAL;
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun 
lp3943_gpio_get(struct gpio_chip * chip,unsigned offset)131*4882a593Smuzhiyun static int lp3943_gpio_get(struct gpio_chip *chip, unsigned offset)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun 	struct lp3943_gpio *lp3943_gpio = gpiochip_get_data(chip);
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	/*
136*4882a593Smuzhiyun 	 * Limitation:
137*4882a593Smuzhiyun 	 *   LP3943 doesn't have the GPIO direction register. It provides
138*4882a593Smuzhiyun 	 *   only input and output status registers.
139*4882a593Smuzhiyun 	 *   So, direction info is required to handle the 'get' operation.
140*4882a593Smuzhiyun 	 *   This variable is updated whenever the direction is changed and
141*4882a593Smuzhiyun 	 *   it is used here.
142*4882a593Smuzhiyun 	 */
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 	if (lp3943_gpio->input_mask & BIT(offset))
145*4882a593Smuzhiyun 		return lp3943_get_gpio_in_status(lp3943_gpio, chip, offset);
146*4882a593Smuzhiyun 	else
147*4882a593Smuzhiyun 		return lp3943_get_gpio_out_status(lp3943_gpio, chip, offset);
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun 
lp3943_gpio_set(struct gpio_chip * chip,unsigned offset,int value)150*4882a593Smuzhiyun static void lp3943_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun 	struct lp3943_gpio *lp3943_gpio = gpiochip_get_data(chip);
153*4882a593Smuzhiyun 	u8 data;
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 	if (value)
156*4882a593Smuzhiyun 		data = LP3943_GPIO_OUT_HIGH;
157*4882a593Smuzhiyun 	else
158*4882a593Smuzhiyun 		data = LP3943_GPIO_OUT_LOW;
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	lp3943_gpio_set_mode(lp3943_gpio, offset, data);
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun 
lp3943_gpio_direction_output(struct gpio_chip * chip,unsigned offset,int value)163*4882a593Smuzhiyun static int lp3943_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
164*4882a593Smuzhiyun 					int value)
165*4882a593Smuzhiyun {
166*4882a593Smuzhiyun 	struct lp3943_gpio *lp3943_gpio = gpiochip_get_data(chip);
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun 	lp3943_gpio_set(chip, offset, value);
169*4882a593Smuzhiyun 	lp3943_gpio->input_mask &= ~BIT(offset);
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun 	return 0;
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun static const struct gpio_chip lp3943_gpio_chip = {
175*4882a593Smuzhiyun 	.label			= "lp3943",
176*4882a593Smuzhiyun 	.owner			= THIS_MODULE,
177*4882a593Smuzhiyun 	.request		= lp3943_gpio_request,
178*4882a593Smuzhiyun 	.free			= lp3943_gpio_free,
179*4882a593Smuzhiyun 	.direction_input	= lp3943_gpio_direction_input,
180*4882a593Smuzhiyun 	.get			= lp3943_gpio_get,
181*4882a593Smuzhiyun 	.direction_output	= lp3943_gpio_direction_output,
182*4882a593Smuzhiyun 	.set			= lp3943_gpio_set,
183*4882a593Smuzhiyun 	.base			= -1,
184*4882a593Smuzhiyun 	.ngpio			= LP3943_MAX_GPIO,
185*4882a593Smuzhiyun 	.can_sleep		= 1,
186*4882a593Smuzhiyun };
187*4882a593Smuzhiyun 
lp3943_gpio_probe(struct platform_device * pdev)188*4882a593Smuzhiyun static int lp3943_gpio_probe(struct platform_device *pdev)
189*4882a593Smuzhiyun {
190*4882a593Smuzhiyun 	struct lp3943 *lp3943 = dev_get_drvdata(pdev->dev.parent);
191*4882a593Smuzhiyun 	struct lp3943_gpio *lp3943_gpio;
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 	lp3943_gpio = devm_kzalloc(&pdev->dev, sizeof(*lp3943_gpio),
194*4882a593Smuzhiyun 				GFP_KERNEL);
195*4882a593Smuzhiyun 	if (!lp3943_gpio)
196*4882a593Smuzhiyun 		return -ENOMEM;
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 	lp3943_gpio->lp3943 = lp3943;
199*4882a593Smuzhiyun 	lp3943_gpio->chip = lp3943_gpio_chip;
200*4882a593Smuzhiyun 	lp3943_gpio->chip.parent = &pdev->dev;
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 	platform_set_drvdata(pdev, lp3943_gpio);
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun 	return devm_gpiochip_add_data(&pdev->dev, &lp3943_gpio->chip,
205*4882a593Smuzhiyun 				      lp3943_gpio);
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun static const struct of_device_id lp3943_gpio_of_match[] = {
209*4882a593Smuzhiyun 	{ .compatible = "ti,lp3943-gpio", },
210*4882a593Smuzhiyun 	{ }
211*4882a593Smuzhiyun };
212*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, lp3943_gpio_of_match);
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun static struct platform_driver lp3943_gpio_driver = {
215*4882a593Smuzhiyun 	.probe = lp3943_gpio_probe,
216*4882a593Smuzhiyun 	.driver = {
217*4882a593Smuzhiyun 		.name = "lp3943-gpio",
218*4882a593Smuzhiyun 		.of_match_table = lp3943_gpio_of_match,
219*4882a593Smuzhiyun 	},
220*4882a593Smuzhiyun };
221*4882a593Smuzhiyun module_platform_driver(lp3943_gpio_driver);
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun MODULE_DESCRIPTION("LP3943 GPIO driver");
224*4882a593Smuzhiyun MODULE_ALIAS("platform:lp3943-gpio");
225*4882a593Smuzhiyun MODULE_AUTHOR("Milo Kim");
226*4882a593Smuzhiyun MODULE_LICENSE("GPL");
227