xref: /OK3568_Linux_fs/kernel/drivers/gpio/gpio-htc-egpio.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Support for the GPIO/IRQ expander chips present on several HTC phones.
3*4882a593Smuzhiyun  * These are implemented in CPLD chips present on the board.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (c) 2007 Kevin O'Connor <kevin@koconnor.net>
6*4882a593Smuzhiyun  * Copyright (c) 2007 Philipp Zabel <philipp.zabel@gmail.com>
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * This file may be distributed under the terms of the GNU GPL license.
9*4882a593Smuzhiyun  */
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/errno.h>
13*4882a593Smuzhiyun #include <linux/interrupt.h>
14*4882a593Smuzhiyun #include <linux/irq.h>
15*4882a593Smuzhiyun #include <linux/io.h>
16*4882a593Smuzhiyun #include <linux/spinlock.h>
17*4882a593Smuzhiyun #include <linux/platform_data/gpio-htc-egpio.h>
18*4882a593Smuzhiyun #include <linux/platform_device.h>
19*4882a593Smuzhiyun #include <linux/slab.h>
20*4882a593Smuzhiyun #include <linux/init.h>
21*4882a593Smuzhiyun #include <linux/gpio/driver.h>
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun struct egpio_chip {
24*4882a593Smuzhiyun 	int              reg_start;
25*4882a593Smuzhiyun 	int              cached_values;
26*4882a593Smuzhiyun 	unsigned long    is_out;
27*4882a593Smuzhiyun 	struct device    *dev;
28*4882a593Smuzhiyun 	struct gpio_chip chip;
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun struct egpio_info {
32*4882a593Smuzhiyun 	spinlock_t        lock;
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun 	/* iomem info */
35*4882a593Smuzhiyun 	void __iomem      *base_addr;
36*4882a593Smuzhiyun 	int               bus_shift;	/* byte shift */
37*4882a593Smuzhiyun 	int               reg_shift;	/* bit shift */
38*4882a593Smuzhiyun 	int               reg_mask;
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun 	/* irq info */
41*4882a593Smuzhiyun 	int               ack_register;
42*4882a593Smuzhiyun 	int               ack_write;
43*4882a593Smuzhiyun 	u16               irqs_enabled;
44*4882a593Smuzhiyun 	uint              irq_start;
45*4882a593Smuzhiyun 	int               nirqs;
46*4882a593Smuzhiyun 	uint              chained_irq;
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun 	/* egpio info */
49*4882a593Smuzhiyun 	struct egpio_chip *chip;
50*4882a593Smuzhiyun 	int               nchips;
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun 
egpio_writew(u16 value,struct egpio_info * ei,int reg)53*4882a593Smuzhiyun static inline void egpio_writew(u16 value, struct egpio_info *ei, int reg)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun 	writew(value, ei->base_addr + (reg << ei->bus_shift));
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun 
egpio_readw(struct egpio_info * ei,int reg)58*4882a593Smuzhiyun static inline u16 egpio_readw(struct egpio_info *ei, int reg)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun 	return readw(ei->base_addr + (reg << ei->bus_shift));
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun /*
64*4882a593Smuzhiyun  * IRQs
65*4882a593Smuzhiyun  */
66*4882a593Smuzhiyun 
ack_irqs(struct egpio_info * ei)67*4882a593Smuzhiyun static inline void ack_irqs(struct egpio_info *ei)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun 	egpio_writew(ei->ack_write, ei, ei->ack_register);
70*4882a593Smuzhiyun 	pr_debug("EGPIO ack - write %x to base+%x\n",
71*4882a593Smuzhiyun 			ei->ack_write, ei->ack_register << ei->bus_shift);
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun 
egpio_ack(struct irq_data * data)74*4882a593Smuzhiyun static void egpio_ack(struct irq_data *data)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun /* There does not appear to be a way to proactively mask interrupts
79*4882a593Smuzhiyun  * on the egpio chip itself.  So, we simply ignore interrupts that
80*4882a593Smuzhiyun  * aren't desired. */
egpio_mask(struct irq_data * data)81*4882a593Smuzhiyun static void egpio_mask(struct irq_data *data)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun 	struct egpio_info *ei = irq_data_get_irq_chip_data(data);
84*4882a593Smuzhiyun 	ei->irqs_enabled &= ~(1 << (data->irq - ei->irq_start));
85*4882a593Smuzhiyun 	pr_debug("EGPIO mask %d %04x\n", data->irq, ei->irqs_enabled);
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun 
egpio_unmask(struct irq_data * data)88*4882a593Smuzhiyun static void egpio_unmask(struct irq_data *data)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun 	struct egpio_info *ei = irq_data_get_irq_chip_data(data);
91*4882a593Smuzhiyun 	ei->irqs_enabled |= 1 << (data->irq - ei->irq_start);
92*4882a593Smuzhiyun 	pr_debug("EGPIO unmask %d %04x\n", data->irq, ei->irqs_enabled);
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun static struct irq_chip egpio_muxed_chip = {
96*4882a593Smuzhiyun 	.name		= "htc-egpio",
97*4882a593Smuzhiyun 	.irq_ack	= egpio_ack,
98*4882a593Smuzhiyun 	.irq_mask	= egpio_mask,
99*4882a593Smuzhiyun 	.irq_unmask	= egpio_unmask,
100*4882a593Smuzhiyun };
101*4882a593Smuzhiyun 
egpio_handler(struct irq_desc * desc)102*4882a593Smuzhiyun static void egpio_handler(struct irq_desc *desc)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun 	struct egpio_info *ei = irq_desc_get_handler_data(desc);
105*4882a593Smuzhiyun 	int irqpin;
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 	/* Read current pins. */
108*4882a593Smuzhiyun 	unsigned long readval = egpio_readw(ei, ei->ack_register);
109*4882a593Smuzhiyun 	pr_debug("IRQ reg: %x\n", (unsigned int)readval);
110*4882a593Smuzhiyun 	/* Ack/unmask interrupts. */
111*4882a593Smuzhiyun 	ack_irqs(ei);
112*4882a593Smuzhiyun 	/* Process all set pins. */
113*4882a593Smuzhiyun 	readval &= ei->irqs_enabled;
114*4882a593Smuzhiyun 	for_each_set_bit(irqpin, &readval, ei->nirqs) {
115*4882a593Smuzhiyun 		/* Run irq handler */
116*4882a593Smuzhiyun 		pr_debug("got IRQ %d\n", irqpin);
117*4882a593Smuzhiyun 		generic_handle_irq(ei->irq_start + irqpin);
118*4882a593Smuzhiyun 	}
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun 
egpio_pos(struct egpio_info * ei,int bit)121*4882a593Smuzhiyun static inline int egpio_pos(struct egpio_info *ei, int bit)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun 	return bit >> ei->reg_shift;
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun 
egpio_bit(struct egpio_info * ei,int bit)126*4882a593Smuzhiyun static inline int egpio_bit(struct egpio_info *ei, int bit)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun 	return 1 << (bit & ((1 << ei->reg_shift)-1));
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun /*
132*4882a593Smuzhiyun  * Input pins
133*4882a593Smuzhiyun  */
134*4882a593Smuzhiyun 
egpio_get(struct gpio_chip * chip,unsigned offset)135*4882a593Smuzhiyun static int egpio_get(struct gpio_chip *chip, unsigned offset)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun 	struct egpio_chip *egpio;
138*4882a593Smuzhiyun 	struct egpio_info *ei;
139*4882a593Smuzhiyun 	unsigned           bit;
140*4882a593Smuzhiyun 	int                reg;
141*4882a593Smuzhiyun 	int                value;
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	pr_debug("egpio_get_value(%d)\n", chip->base + offset);
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun 	egpio = gpiochip_get_data(chip);
146*4882a593Smuzhiyun 	ei    = dev_get_drvdata(egpio->dev);
147*4882a593Smuzhiyun 	bit   = egpio_bit(ei, offset);
148*4882a593Smuzhiyun 	reg   = egpio->reg_start + egpio_pos(ei, offset);
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	if (test_bit(offset, &egpio->is_out)) {
151*4882a593Smuzhiyun 		return !!(egpio->cached_values & (1 << offset));
152*4882a593Smuzhiyun 	} else {
153*4882a593Smuzhiyun 		value = egpio_readw(ei, reg);
154*4882a593Smuzhiyun 		pr_debug("readw(%p + %x) = %x\n",
155*4882a593Smuzhiyun 			 ei->base_addr, reg << ei->bus_shift, value);
156*4882a593Smuzhiyun 		return !!(value & bit);
157*4882a593Smuzhiyun 	}
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun 
egpio_direction_input(struct gpio_chip * chip,unsigned offset)160*4882a593Smuzhiyun static int egpio_direction_input(struct gpio_chip *chip, unsigned offset)
161*4882a593Smuzhiyun {
162*4882a593Smuzhiyun 	struct egpio_chip *egpio;
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	egpio = gpiochip_get_data(chip);
165*4882a593Smuzhiyun 	return test_bit(offset, &egpio->is_out) ? -EINVAL : 0;
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun /*
170*4882a593Smuzhiyun  * Output pins
171*4882a593Smuzhiyun  */
172*4882a593Smuzhiyun 
egpio_set(struct gpio_chip * chip,unsigned offset,int value)173*4882a593Smuzhiyun static void egpio_set(struct gpio_chip *chip, unsigned offset, int value)
174*4882a593Smuzhiyun {
175*4882a593Smuzhiyun 	unsigned long     flag;
176*4882a593Smuzhiyun 	struct egpio_chip *egpio;
177*4882a593Smuzhiyun 	struct egpio_info *ei;
178*4882a593Smuzhiyun 	int               pos;
179*4882a593Smuzhiyun 	int               reg;
180*4882a593Smuzhiyun 	int               shift;
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 	pr_debug("egpio_set(%s, %d(%d), %d)\n",
183*4882a593Smuzhiyun 			chip->label, offset, offset+chip->base, value);
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 	egpio = gpiochip_get_data(chip);
186*4882a593Smuzhiyun 	ei    = dev_get_drvdata(egpio->dev);
187*4882a593Smuzhiyun 	pos   = egpio_pos(ei, offset);
188*4882a593Smuzhiyun 	reg   = egpio->reg_start + pos;
189*4882a593Smuzhiyun 	shift = pos << ei->reg_shift;
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 	pr_debug("egpio %s: reg %d = 0x%04x\n", value ? "set" : "clear",
192*4882a593Smuzhiyun 			reg, (egpio->cached_values >> shift) & ei->reg_mask);
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 	spin_lock_irqsave(&ei->lock, flag);
195*4882a593Smuzhiyun 	if (value)
196*4882a593Smuzhiyun 		egpio->cached_values |= (1 << offset);
197*4882a593Smuzhiyun 	else
198*4882a593Smuzhiyun 		egpio->cached_values &= ~(1 << offset);
199*4882a593Smuzhiyun 	egpio_writew((egpio->cached_values >> shift) & ei->reg_mask, ei, reg);
200*4882a593Smuzhiyun 	spin_unlock_irqrestore(&ei->lock, flag);
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun 
egpio_direction_output(struct gpio_chip * chip,unsigned offset,int value)203*4882a593Smuzhiyun static int egpio_direction_output(struct gpio_chip *chip,
204*4882a593Smuzhiyun 					unsigned offset, int value)
205*4882a593Smuzhiyun {
206*4882a593Smuzhiyun 	struct egpio_chip *egpio;
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun 	egpio = gpiochip_get_data(chip);
209*4882a593Smuzhiyun 	if (test_bit(offset, &egpio->is_out)) {
210*4882a593Smuzhiyun 		egpio_set(chip, offset, value);
211*4882a593Smuzhiyun 		return 0;
212*4882a593Smuzhiyun 	} else {
213*4882a593Smuzhiyun 		return -EINVAL;
214*4882a593Smuzhiyun 	}
215*4882a593Smuzhiyun }
216*4882a593Smuzhiyun 
egpio_get_direction(struct gpio_chip * chip,unsigned offset)217*4882a593Smuzhiyun static int egpio_get_direction(struct gpio_chip *chip, unsigned offset)
218*4882a593Smuzhiyun {
219*4882a593Smuzhiyun 	struct egpio_chip *egpio;
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun 	egpio = gpiochip_get_data(chip);
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun 	if (test_bit(offset, &egpio->is_out))
224*4882a593Smuzhiyun 		return GPIO_LINE_DIRECTION_OUT;
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun 	return GPIO_LINE_DIRECTION_IN;
227*4882a593Smuzhiyun }
228*4882a593Smuzhiyun 
egpio_write_cache(struct egpio_info * ei)229*4882a593Smuzhiyun static void egpio_write_cache(struct egpio_info *ei)
230*4882a593Smuzhiyun {
231*4882a593Smuzhiyun 	int               i;
232*4882a593Smuzhiyun 	struct egpio_chip *egpio;
233*4882a593Smuzhiyun 	int               shift;
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun 	for (i = 0; i < ei->nchips; i++) {
236*4882a593Smuzhiyun 		egpio = &(ei->chip[i]);
237*4882a593Smuzhiyun 		if (!egpio->is_out)
238*4882a593Smuzhiyun 			continue;
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun 		for (shift = 0; shift < egpio->chip.ngpio;
241*4882a593Smuzhiyun 				shift += (1<<ei->reg_shift)) {
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun 			int reg = egpio->reg_start + egpio_pos(ei, shift);
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 			if (!((egpio->is_out >> shift) & ei->reg_mask))
246*4882a593Smuzhiyun 				continue;
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 			pr_debug("EGPIO: setting %x to %x, was %x\n", reg,
249*4882a593Smuzhiyun 				(egpio->cached_values >> shift) & ei->reg_mask,
250*4882a593Smuzhiyun 				egpio_readw(ei, reg));
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun 			egpio_writew((egpio->cached_values >> shift)
253*4882a593Smuzhiyun 					& ei->reg_mask, ei, reg);
254*4882a593Smuzhiyun 		}
255*4882a593Smuzhiyun 	}
256*4882a593Smuzhiyun }
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun /*
260*4882a593Smuzhiyun  * Setup
261*4882a593Smuzhiyun  */
262*4882a593Smuzhiyun 
egpio_probe(struct platform_device * pdev)263*4882a593Smuzhiyun static int __init egpio_probe(struct platform_device *pdev)
264*4882a593Smuzhiyun {
265*4882a593Smuzhiyun 	struct htc_egpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
266*4882a593Smuzhiyun 	struct resource   *res;
267*4882a593Smuzhiyun 	struct egpio_info *ei;
268*4882a593Smuzhiyun 	struct gpio_chip  *chip;
269*4882a593Smuzhiyun 	unsigned int      irq, irq_end;
270*4882a593Smuzhiyun 	int               i;
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun 	/* Initialize ei data structure. */
273*4882a593Smuzhiyun 	ei = devm_kzalloc(&pdev->dev, sizeof(*ei), GFP_KERNEL);
274*4882a593Smuzhiyun 	if (!ei)
275*4882a593Smuzhiyun 		return -ENOMEM;
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun 	spin_lock_init(&ei->lock);
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun 	/* Find chained irq */
280*4882a593Smuzhiyun 	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
281*4882a593Smuzhiyun 	if (res)
282*4882a593Smuzhiyun 		ei->chained_irq = res->start;
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun 	/* Map egpio chip into virtual address space. */
285*4882a593Smuzhiyun 	ei->base_addr = devm_platform_ioremap_resource(pdev, 0);
286*4882a593Smuzhiyun 	if (IS_ERR(ei->base_addr))
287*4882a593Smuzhiyun 		return PTR_ERR(ei->base_addr);
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun 	if ((pdata->bus_width != 16) && (pdata->bus_width != 32))
290*4882a593Smuzhiyun 		return -EINVAL;
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun 	ei->bus_shift = fls(pdata->bus_width - 1) - 3;
293*4882a593Smuzhiyun 	pr_debug("bus_shift = %d\n", ei->bus_shift);
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun 	if ((pdata->reg_width != 8) && (pdata->reg_width != 16))
296*4882a593Smuzhiyun 		return -EINVAL;
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun 	ei->reg_shift = fls(pdata->reg_width - 1);
299*4882a593Smuzhiyun 	pr_debug("reg_shift = %d\n", ei->reg_shift);
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun 	ei->reg_mask = (1 << pdata->reg_width) - 1;
302*4882a593Smuzhiyun 
303*4882a593Smuzhiyun 	platform_set_drvdata(pdev, ei);
304*4882a593Smuzhiyun 
305*4882a593Smuzhiyun 	ei->nchips = pdata->num_chips;
306*4882a593Smuzhiyun 	ei->chip = devm_kcalloc(&pdev->dev,
307*4882a593Smuzhiyun 				ei->nchips, sizeof(struct egpio_chip),
308*4882a593Smuzhiyun 				GFP_KERNEL);
309*4882a593Smuzhiyun 	if (!ei->chip)
310*4882a593Smuzhiyun 		return -ENOMEM;
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun 	for (i = 0; i < ei->nchips; i++) {
313*4882a593Smuzhiyun 		ei->chip[i].reg_start = pdata->chip[i].reg_start;
314*4882a593Smuzhiyun 		ei->chip[i].cached_values = pdata->chip[i].initial_values;
315*4882a593Smuzhiyun 		ei->chip[i].is_out = pdata->chip[i].direction;
316*4882a593Smuzhiyun 		ei->chip[i].dev = &(pdev->dev);
317*4882a593Smuzhiyun 		chip = &(ei->chip[i].chip);
318*4882a593Smuzhiyun 		chip->label = devm_kasprintf(&pdev->dev, GFP_KERNEL,
319*4882a593Smuzhiyun 					     "htc-egpio-%d",
320*4882a593Smuzhiyun 					     i);
321*4882a593Smuzhiyun 		if (!chip->label)
322*4882a593Smuzhiyun 			return -ENOMEM;
323*4882a593Smuzhiyun 
324*4882a593Smuzhiyun 		chip->parent          = &pdev->dev;
325*4882a593Smuzhiyun 		chip->owner           = THIS_MODULE;
326*4882a593Smuzhiyun 		chip->get             = egpio_get;
327*4882a593Smuzhiyun 		chip->set             = egpio_set;
328*4882a593Smuzhiyun 		chip->direction_input = egpio_direction_input;
329*4882a593Smuzhiyun 		chip->direction_output = egpio_direction_output;
330*4882a593Smuzhiyun 		chip->get_direction   = egpio_get_direction;
331*4882a593Smuzhiyun 		chip->base            = pdata->chip[i].gpio_base;
332*4882a593Smuzhiyun 		chip->ngpio           = pdata->chip[i].num_gpios;
333*4882a593Smuzhiyun 
334*4882a593Smuzhiyun 		gpiochip_add_data(chip, &ei->chip[i]);
335*4882a593Smuzhiyun 	}
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun 	/* Set initial pin values */
338*4882a593Smuzhiyun 	egpio_write_cache(ei);
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun 	ei->irq_start = pdata->irq_base;
341*4882a593Smuzhiyun 	ei->nirqs = pdata->num_irqs;
342*4882a593Smuzhiyun 	ei->ack_register = pdata->ack_register;
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun 	if (ei->chained_irq) {
345*4882a593Smuzhiyun 		/* Setup irq handlers */
346*4882a593Smuzhiyun 		ei->ack_write = 0xFFFF;
347*4882a593Smuzhiyun 		if (pdata->invert_acks)
348*4882a593Smuzhiyun 			ei->ack_write = 0;
349*4882a593Smuzhiyun 		irq_end = ei->irq_start + ei->nirqs;
350*4882a593Smuzhiyun 		for (irq = ei->irq_start; irq < irq_end; irq++) {
351*4882a593Smuzhiyun 			irq_set_chip_and_handler(irq, &egpio_muxed_chip,
352*4882a593Smuzhiyun 						 handle_simple_irq);
353*4882a593Smuzhiyun 			irq_set_chip_data(irq, ei);
354*4882a593Smuzhiyun 			irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
355*4882a593Smuzhiyun 		}
356*4882a593Smuzhiyun 		irq_set_irq_type(ei->chained_irq, IRQ_TYPE_EDGE_RISING);
357*4882a593Smuzhiyun 		irq_set_chained_handler_and_data(ei->chained_irq,
358*4882a593Smuzhiyun 						 egpio_handler, ei);
359*4882a593Smuzhiyun 		ack_irqs(ei);
360*4882a593Smuzhiyun 
361*4882a593Smuzhiyun 		device_init_wakeup(&pdev->dev, 1);
362*4882a593Smuzhiyun 	}
363*4882a593Smuzhiyun 
364*4882a593Smuzhiyun 	return 0;
365*4882a593Smuzhiyun }
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun #ifdef CONFIG_PM
egpio_suspend(struct platform_device * pdev,pm_message_t state)368*4882a593Smuzhiyun static int egpio_suspend(struct platform_device *pdev, pm_message_t state)
369*4882a593Smuzhiyun {
370*4882a593Smuzhiyun 	struct egpio_info *ei = platform_get_drvdata(pdev);
371*4882a593Smuzhiyun 
372*4882a593Smuzhiyun 	if (ei->chained_irq && device_may_wakeup(&pdev->dev))
373*4882a593Smuzhiyun 		enable_irq_wake(ei->chained_irq);
374*4882a593Smuzhiyun 	return 0;
375*4882a593Smuzhiyun }
376*4882a593Smuzhiyun 
egpio_resume(struct platform_device * pdev)377*4882a593Smuzhiyun static int egpio_resume(struct platform_device *pdev)
378*4882a593Smuzhiyun {
379*4882a593Smuzhiyun 	struct egpio_info *ei = platform_get_drvdata(pdev);
380*4882a593Smuzhiyun 
381*4882a593Smuzhiyun 	if (ei->chained_irq && device_may_wakeup(&pdev->dev))
382*4882a593Smuzhiyun 		disable_irq_wake(ei->chained_irq);
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun 	/* Update registers from the cache, in case
385*4882a593Smuzhiyun 	   the CPLD was powered off during suspend */
386*4882a593Smuzhiyun 	egpio_write_cache(ei);
387*4882a593Smuzhiyun 	return 0;
388*4882a593Smuzhiyun }
389*4882a593Smuzhiyun #else
390*4882a593Smuzhiyun #define egpio_suspend NULL
391*4882a593Smuzhiyun #define egpio_resume NULL
392*4882a593Smuzhiyun #endif
393*4882a593Smuzhiyun 
394*4882a593Smuzhiyun 
395*4882a593Smuzhiyun static struct platform_driver egpio_driver = {
396*4882a593Smuzhiyun 	.driver = {
397*4882a593Smuzhiyun 		.name = "htc-egpio",
398*4882a593Smuzhiyun 		.suppress_bind_attrs = true,
399*4882a593Smuzhiyun 	},
400*4882a593Smuzhiyun 	.suspend      = egpio_suspend,
401*4882a593Smuzhiyun 	.resume       = egpio_resume,
402*4882a593Smuzhiyun };
403*4882a593Smuzhiyun 
egpio_init(void)404*4882a593Smuzhiyun static int __init egpio_init(void)
405*4882a593Smuzhiyun {
406*4882a593Smuzhiyun 	return platform_driver_probe(&egpio_driver, egpio_probe);
407*4882a593Smuzhiyun }
408*4882a593Smuzhiyun /* start early for dependencies */
409*4882a593Smuzhiyun subsys_initcall(egpio_init);
410