xref: /OK3568_Linux_fs/kernel/drivers/gpio/gpio-bd71828.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun // Copyright (C) 2018 ROHM Semiconductors
3*4882a593Smuzhiyun 
4*4882a593Smuzhiyun #include <linux/gpio/driver.h>
5*4882a593Smuzhiyun #include <linux/mfd/rohm-bd71828.h>
6*4882a593Smuzhiyun #include <linux/module.h>
7*4882a593Smuzhiyun #include <linux/platform_device.h>
8*4882a593Smuzhiyun #include <linux/regmap.h>
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #define GPIO_OUT_REG(off) (BD71828_REG_GPIO_CTRL1 + (off))
11*4882a593Smuzhiyun #define HALL_GPIO_OFFSET 3
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun struct bd71828_gpio {
14*4882a593Smuzhiyun 	struct rohm_regmap_dev chip;
15*4882a593Smuzhiyun 	struct gpio_chip gpio;
16*4882a593Smuzhiyun };
17*4882a593Smuzhiyun 
bd71828_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)18*4882a593Smuzhiyun static void bd71828_gpio_set(struct gpio_chip *chip, unsigned int offset,
19*4882a593Smuzhiyun 			     int value)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun 	int ret;
22*4882a593Smuzhiyun 	struct bd71828_gpio *bdgpio = gpiochip_get_data(chip);
23*4882a593Smuzhiyun 	u8 val = (value) ? BD71828_GPIO_OUT_HI : BD71828_GPIO_OUT_LO;
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun 	/*
26*4882a593Smuzhiyun 	 * The HALL input pin can only be used as input. If this is the pin
27*4882a593Smuzhiyun 	 * we are dealing with - then we are done
28*4882a593Smuzhiyun 	 */
29*4882a593Smuzhiyun 	if (offset == HALL_GPIO_OFFSET)
30*4882a593Smuzhiyun 		return;
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun 	ret = regmap_update_bits(bdgpio->chip.regmap, GPIO_OUT_REG(offset),
33*4882a593Smuzhiyun 				 BD71828_GPIO_OUT_MASK, val);
34*4882a593Smuzhiyun 	if (ret)
35*4882a593Smuzhiyun 		dev_err(bdgpio->chip.dev, "Could not set gpio to %d\n", value);
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun 
bd71828_gpio_get(struct gpio_chip * chip,unsigned int offset)38*4882a593Smuzhiyun static int bd71828_gpio_get(struct gpio_chip *chip, unsigned int offset)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun 	int ret;
41*4882a593Smuzhiyun 	unsigned int val;
42*4882a593Smuzhiyun 	struct bd71828_gpio *bdgpio = gpiochip_get_data(chip);
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun 	if (offset == HALL_GPIO_OFFSET)
45*4882a593Smuzhiyun 		ret = regmap_read(bdgpio->chip.regmap, BD71828_REG_IO_STAT,
46*4882a593Smuzhiyun 				  &val);
47*4882a593Smuzhiyun 	else
48*4882a593Smuzhiyun 		ret = regmap_read(bdgpio->chip.regmap, GPIO_OUT_REG(offset),
49*4882a593Smuzhiyun 				  &val);
50*4882a593Smuzhiyun 	if (!ret)
51*4882a593Smuzhiyun 		ret = (val & BD71828_GPIO_OUT_MASK);
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun 	return ret;
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun 
bd71828_gpio_set_config(struct gpio_chip * chip,unsigned int offset,unsigned long config)56*4882a593Smuzhiyun static int bd71828_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
57*4882a593Smuzhiyun 				   unsigned long config)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun 	struct bd71828_gpio *bdgpio = gpiochip_get_data(chip);
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun 	if (offset == HALL_GPIO_OFFSET)
62*4882a593Smuzhiyun 		return -ENOTSUPP;
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun 	switch (pinconf_to_config_param(config)) {
65*4882a593Smuzhiyun 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
66*4882a593Smuzhiyun 		return regmap_update_bits(bdgpio->chip.regmap,
67*4882a593Smuzhiyun 					  GPIO_OUT_REG(offset),
68*4882a593Smuzhiyun 					  BD71828_GPIO_DRIVE_MASK,
69*4882a593Smuzhiyun 					  BD71828_GPIO_OPEN_DRAIN);
70*4882a593Smuzhiyun 	case PIN_CONFIG_DRIVE_PUSH_PULL:
71*4882a593Smuzhiyun 		return regmap_update_bits(bdgpio->chip.regmap,
72*4882a593Smuzhiyun 					  GPIO_OUT_REG(offset),
73*4882a593Smuzhiyun 					  BD71828_GPIO_DRIVE_MASK,
74*4882a593Smuzhiyun 					  BD71828_GPIO_PUSH_PULL);
75*4882a593Smuzhiyun 	default:
76*4882a593Smuzhiyun 		break;
77*4882a593Smuzhiyun 	}
78*4882a593Smuzhiyun 	return -ENOTSUPP;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun 
bd71828_get_direction(struct gpio_chip * chip,unsigned int offset)81*4882a593Smuzhiyun static int bd71828_get_direction(struct gpio_chip *chip, unsigned int offset)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun 	/*
84*4882a593Smuzhiyun 	 * Pin usage is selected by OTP data. We can't read it runtime. Hence
85*4882a593Smuzhiyun 	 * we trust that if the pin is not excluded by "gpio-reserved-ranges"
86*4882a593Smuzhiyun 	 * the OTP configuration is set to OUT. (Other pins but HALL input pin
87*4882a593Smuzhiyun 	 * on BD71828 can't really be used for general purpose input - input
88*4882a593Smuzhiyun 	 * states are used for specific cases like regulator control or
89*4882a593Smuzhiyun 	 * PMIC_ON_REQ.
90*4882a593Smuzhiyun 	 */
91*4882a593Smuzhiyun 	if (offset == HALL_GPIO_OFFSET)
92*4882a593Smuzhiyun 		return GPIO_LINE_DIRECTION_IN;
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 	return GPIO_LINE_DIRECTION_OUT;
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun 
bd71828_probe(struct platform_device * pdev)97*4882a593Smuzhiyun static int bd71828_probe(struct platform_device *pdev)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun 	struct bd71828_gpio *bdgpio;
100*4882a593Smuzhiyun 	struct rohm_regmap_dev *bd71828;
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 	bd71828 = dev_get_drvdata(pdev->dev.parent);
103*4882a593Smuzhiyun 	if (!bd71828) {
104*4882a593Smuzhiyun 		dev_err(&pdev->dev, "No MFD driver data\n");
105*4882a593Smuzhiyun 		return -EINVAL;
106*4882a593Smuzhiyun 	}
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	bdgpio = devm_kzalloc(&pdev->dev, sizeof(*bdgpio),
109*4882a593Smuzhiyun 			      GFP_KERNEL);
110*4882a593Smuzhiyun 	if (!bdgpio)
111*4882a593Smuzhiyun 		return -ENOMEM;
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	bdgpio->chip.dev = &pdev->dev;
114*4882a593Smuzhiyun 	bdgpio->gpio.parent = pdev->dev.parent;
115*4882a593Smuzhiyun 	bdgpio->gpio.label = "bd71828-gpio";
116*4882a593Smuzhiyun 	bdgpio->gpio.owner = THIS_MODULE;
117*4882a593Smuzhiyun 	bdgpio->gpio.get_direction = bd71828_get_direction;
118*4882a593Smuzhiyun 	bdgpio->gpio.set_config = bd71828_gpio_set_config;
119*4882a593Smuzhiyun 	bdgpio->gpio.can_sleep = true;
120*4882a593Smuzhiyun 	bdgpio->gpio.get = bd71828_gpio_get;
121*4882a593Smuzhiyun 	bdgpio->gpio.set = bd71828_gpio_set;
122*4882a593Smuzhiyun 	bdgpio->gpio.base = -1;
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	/*
125*4882a593Smuzhiyun 	 * See if we need some implementation to mark some PINs as
126*4882a593Smuzhiyun 	 * not controllable based on DT info or if core can handle
127*4882a593Smuzhiyun 	 * "gpio-reserved-ranges" and exclude them from control
128*4882a593Smuzhiyun 	 */
129*4882a593Smuzhiyun 	bdgpio->gpio.ngpio = 4;
130*4882a593Smuzhiyun 	bdgpio->gpio.of_node = pdev->dev.parent->of_node;
131*4882a593Smuzhiyun 	bdgpio->chip.regmap = bd71828->regmap;
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	return devm_gpiochip_add_data(&pdev->dev, &bdgpio->gpio,
134*4882a593Smuzhiyun 				     bdgpio);
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun static struct platform_driver bd71828_gpio = {
138*4882a593Smuzhiyun 	.driver = {
139*4882a593Smuzhiyun 		.name = "bd71828-gpio"
140*4882a593Smuzhiyun 	},
141*4882a593Smuzhiyun 	.probe = bd71828_probe,
142*4882a593Smuzhiyun };
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun module_platform_driver(bd71828_gpio);
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>");
147*4882a593Smuzhiyun MODULE_DESCRIPTION("BD71828 voltage regulator driver");
148*4882a593Smuzhiyun MODULE_LICENSE("GPL");
149*4882a593Smuzhiyun MODULE_ALIAS("platform:bd71828-gpio");
150