1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * GPIO Chip driver for Analog Devices
4*4882a593Smuzhiyun * ADP5588/ADP5587 I/O Expander and QWERTY Keypad Controller
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright 2009-2010 Analog Devices Inc.
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/kernel.h>
11*4882a593Smuzhiyun #include <linux/slab.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/i2c.h>
14*4882a593Smuzhiyun #include <linux/gpio/driver.h>
15*4882a593Smuzhiyun #include <linux/interrupt.h>
16*4882a593Smuzhiyun #include <linux/irq.h>
17*4882a593Smuzhiyun #include <linux/of_device.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include <linux/platform_data/adp5588.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define DRV_NAME "adp5588-gpio"
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /*
24*4882a593Smuzhiyun * Early pre 4.0 Silicon required to delay readout by at least 25ms,
25*4882a593Smuzhiyun * since the Event Counter Register updated 25ms after the interrupt
26*4882a593Smuzhiyun * asserted.
27*4882a593Smuzhiyun */
28*4882a593Smuzhiyun #define WA_DELAYED_READOUT_REVID(rev) ((rev) < 4)
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun struct adp5588_gpio {
31*4882a593Smuzhiyun struct i2c_client *client;
32*4882a593Smuzhiyun struct gpio_chip gpio_chip;
33*4882a593Smuzhiyun struct mutex lock; /* protect cached dir, dat_out */
34*4882a593Smuzhiyun /* protect serialized access to the interrupt controller bus */
35*4882a593Smuzhiyun struct mutex irq_lock;
36*4882a593Smuzhiyun uint8_t dat_out[3];
37*4882a593Smuzhiyun uint8_t dir[3];
38*4882a593Smuzhiyun uint8_t int_lvl_low[3];
39*4882a593Smuzhiyun uint8_t int_lvl_high[3];
40*4882a593Smuzhiyun uint8_t int_en[3];
41*4882a593Smuzhiyun uint8_t irq_mask[3];
42*4882a593Smuzhiyun uint8_t int_input_en[3];
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun
adp5588_gpio_read(struct i2c_client * client,u8 reg)45*4882a593Smuzhiyun static int adp5588_gpio_read(struct i2c_client *client, u8 reg)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun int ret = i2c_smbus_read_byte_data(client, reg);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun if (ret < 0)
50*4882a593Smuzhiyun dev_err(&client->dev, "Read Error\n");
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun return ret;
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
adp5588_gpio_write(struct i2c_client * client,u8 reg,u8 val)55*4882a593Smuzhiyun static int adp5588_gpio_write(struct i2c_client *client, u8 reg, u8 val)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun int ret = i2c_smbus_write_byte_data(client, reg, val);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun if (ret < 0)
60*4882a593Smuzhiyun dev_err(&client->dev, "Write Error\n");
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun return ret;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
adp5588_gpio_get_value(struct gpio_chip * chip,unsigned off)65*4882a593Smuzhiyun static int adp5588_gpio_get_value(struct gpio_chip *chip, unsigned off)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun struct adp5588_gpio *dev = gpiochip_get_data(chip);
68*4882a593Smuzhiyun unsigned bank = ADP5588_BANK(off);
69*4882a593Smuzhiyun unsigned bit = ADP5588_BIT(off);
70*4882a593Smuzhiyun int val;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun mutex_lock(&dev->lock);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun if (dev->dir[bank] & bit)
75*4882a593Smuzhiyun val = dev->dat_out[bank];
76*4882a593Smuzhiyun else
77*4882a593Smuzhiyun val = adp5588_gpio_read(dev->client, GPIO_DAT_STAT1 + bank);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun mutex_unlock(&dev->lock);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun return !!(val & bit);
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
adp5588_gpio_set_value(struct gpio_chip * chip,unsigned off,int val)84*4882a593Smuzhiyun static void adp5588_gpio_set_value(struct gpio_chip *chip,
85*4882a593Smuzhiyun unsigned off, int val)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun unsigned bank, bit;
88*4882a593Smuzhiyun struct adp5588_gpio *dev = gpiochip_get_data(chip);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun bank = ADP5588_BANK(off);
91*4882a593Smuzhiyun bit = ADP5588_BIT(off);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun mutex_lock(&dev->lock);
94*4882a593Smuzhiyun if (val)
95*4882a593Smuzhiyun dev->dat_out[bank] |= bit;
96*4882a593Smuzhiyun else
97*4882a593Smuzhiyun dev->dat_out[bank] &= ~bit;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun adp5588_gpio_write(dev->client, GPIO_DAT_OUT1 + bank,
100*4882a593Smuzhiyun dev->dat_out[bank]);
101*4882a593Smuzhiyun mutex_unlock(&dev->lock);
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
adp5588_gpio_direction_input(struct gpio_chip * chip,unsigned off)104*4882a593Smuzhiyun static int adp5588_gpio_direction_input(struct gpio_chip *chip, unsigned off)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun int ret;
107*4882a593Smuzhiyun unsigned bank;
108*4882a593Smuzhiyun struct adp5588_gpio *dev = gpiochip_get_data(chip);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun bank = ADP5588_BANK(off);
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun mutex_lock(&dev->lock);
113*4882a593Smuzhiyun dev->dir[bank] &= ~ADP5588_BIT(off);
114*4882a593Smuzhiyun ret = adp5588_gpio_write(dev->client, GPIO_DIR1 + bank, dev->dir[bank]);
115*4882a593Smuzhiyun mutex_unlock(&dev->lock);
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun return ret;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun
adp5588_gpio_direction_output(struct gpio_chip * chip,unsigned off,int val)120*4882a593Smuzhiyun static int adp5588_gpio_direction_output(struct gpio_chip *chip,
121*4882a593Smuzhiyun unsigned off, int val)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun int ret;
124*4882a593Smuzhiyun unsigned bank, bit;
125*4882a593Smuzhiyun struct adp5588_gpio *dev = gpiochip_get_data(chip);
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun bank = ADP5588_BANK(off);
128*4882a593Smuzhiyun bit = ADP5588_BIT(off);
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun mutex_lock(&dev->lock);
131*4882a593Smuzhiyun dev->dir[bank] |= bit;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun if (val)
134*4882a593Smuzhiyun dev->dat_out[bank] |= bit;
135*4882a593Smuzhiyun else
136*4882a593Smuzhiyun dev->dat_out[bank] &= ~bit;
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun ret = adp5588_gpio_write(dev->client, GPIO_DAT_OUT1 + bank,
139*4882a593Smuzhiyun dev->dat_out[bank]);
140*4882a593Smuzhiyun ret |= adp5588_gpio_write(dev->client, GPIO_DIR1 + bank,
141*4882a593Smuzhiyun dev->dir[bank]);
142*4882a593Smuzhiyun mutex_unlock(&dev->lock);
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun return ret;
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun #ifdef CONFIG_GPIO_ADP5588_IRQ
148*4882a593Smuzhiyun
adp5588_irq_bus_lock(struct irq_data * d)149*4882a593Smuzhiyun static void adp5588_irq_bus_lock(struct irq_data *d)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
152*4882a593Smuzhiyun struct adp5588_gpio *dev = gpiochip_get_data(gc);
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun mutex_lock(&dev->irq_lock);
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun /*
158*4882a593Smuzhiyun * genirq core code can issue chip->mask/unmask from atomic context.
159*4882a593Smuzhiyun * This doesn't work for slow busses where an access needs to sleep.
160*4882a593Smuzhiyun * bus_sync_unlock() is therefore called outside the atomic context,
161*4882a593Smuzhiyun * syncs the current irq mask state with the slow external controller
162*4882a593Smuzhiyun * and unlocks the bus.
163*4882a593Smuzhiyun */
164*4882a593Smuzhiyun
adp5588_irq_bus_sync_unlock(struct irq_data * d)165*4882a593Smuzhiyun static void adp5588_irq_bus_sync_unlock(struct irq_data *d)
166*4882a593Smuzhiyun {
167*4882a593Smuzhiyun struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
168*4882a593Smuzhiyun struct adp5588_gpio *dev = gpiochip_get_data(gc);
169*4882a593Smuzhiyun int i;
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun for (i = 0; i <= ADP5588_BANK(ADP5588_MAXGPIO); i++) {
172*4882a593Smuzhiyun if (dev->int_input_en[i]) {
173*4882a593Smuzhiyun mutex_lock(&dev->lock);
174*4882a593Smuzhiyun dev->dir[i] &= ~dev->int_input_en[i];
175*4882a593Smuzhiyun dev->int_input_en[i] = 0;
176*4882a593Smuzhiyun adp5588_gpio_write(dev->client, GPIO_DIR1 + i,
177*4882a593Smuzhiyun dev->dir[i]);
178*4882a593Smuzhiyun mutex_unlock(&dev->lock);
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun if (dev->int_en[i] ^ dev->irq_mask[i]) {
182*4882a593Smuzhiyun dev->int_en[i] = dev->irq_mask[i];
183*4882a593Smuzhiyun adp5588_gpio_write(dev->client, GPI_EM1 + i,
184*4882a593Smuzhiyun dev->int_en[i]);
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun mutex_unlock(&dev->irq_lock);
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun
adp5588_irq_mask(struct irq_data * d)191*4882a593Smuzhiyun static void adp5588_irq_mask(struct irq_data *d)
192*4882a593Smuzhiyun {
193*4882a593Smuzhiyun struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
194*4882a593Smuzhiyun struct adp5588_gpio *dev = gpiochip_get_data(gc);
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun dev->irq_mask[ADP5588_BANK(d->hwirq)] &= ~ADP5588_BIT(d->hwirq);
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun
adp5588_irq_unmask(struct irq_data * d)199*4882a593Smuzhiyun static void adp5588_irq_unmask(struct irq_data *d)
200*4882a593Smuzhiyun {
201*4882a593Smuzhiyun struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
202*4882a593Smuzhiyun struct adp5588_gpio *dev = gpiochip_get_data(gc);
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun dev->irq_mask[ADP5588_BANK(d->hwirq)] |= ADP5588_BIT(d->hwirq);
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun
adp5588_irq_set_type(struct irq_data * d,unsigned int type)207*4882a593Smuzhiyun static int adp5588_irq_set_type(struct irq_data *d, unsigned int type)
208*4882a593Smuzhiyun {
209*4882a593Smuzhiyun struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
210*4882a593Smuzhiyun struct adp5588_gpio *dev = gpiochip_get_data(gc);
211*4882a593Smuzhiyun uint16_t gpio = d->hwirq;
212*4882a593Smuzhiyun unsigned bank, bit;
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun bank = ADP5588_BANK(gpio);
215*4882a593Smuzhiyun bit = ADP5588_BIT(gpio);
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun dev->int_lvl_low[bank] &= ~bit;
218*4882a593Smuzhiyun dev->int_lvl_high[bank] &= ~bit;
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun if (type & IRQ_TYPE_EDGE_BOTH || type & IRQ_TYPE_LEVEL_HIGH)
221*4882a593Smuzhiyun dev->int_lvl_high[bank] |= bit;
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun if (type & IRQ_TYPE_EDGE_BOTH || type & IRQ_TYPE_LEVEL_LOW)
224*4882a593Smuzhiyun dev->int_lvl_low[bank] |= bit;
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun dev->int_input_en[bank] |= bit;
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun return 0;
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun static struct irq_chip adp5588_irq_chip = {
232*4882a593Smuzhiyun .name = "adp5588",
233*4882a593Smuzhiyun .irq_mask = adp5588_irq_mask,
234*4882a593Smuzhiyun .irq_unmask = adp5588_irq_unmask,
235*4882a593Smuzhiyun .irq_bus_lock = adp5588_irq_bus_lock,
236*4882a593Smuzhiyun .irq_bus_sync_unlock = adp5588_irq_bus_sync_unlock,
237*4882a593Smuzhiyun .irq_set_type = adp5588_irq_set_type,
238*4882a593Smuzhiyun };
239*4882a593Smuzhiyun
adp5588_irq_handler(int irq,void * devid)240*4882a593Smuzhiyun static irqreturn_t adp5588_irq_handler(int irq, void *devid)
241*4882a593Smuzhiyun {
242*4882a593Smuzhiyun struct adp5588_gpio *dev = devid;
243*4882a593Smuzhiyun int status = adp5588_gpio_read(dev->client, INT_STAT);
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun if (status & ADP5588_KE_INT) {
246*4882a593Smuzhiyun int ev_cnt = adp5588_gpio_read(dev->client, KEY_LCK_EC_STAT);
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun if (ev_cnt > 0) {
249*4882a593Smuzhiyun int i;
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun for (i = 0; i < (ev_cnt & ADP5588_KEC); i++) {
252*4882a593Smuzhiyun int key = adp5588_gpio_read(dev->client,
253*4882a593Smuzhiyun Key_EVENTA + i);
254*4882a593Smuzhiyun /* GPIN events begin at 97,
255*4882a593Smuzhiyun * bit 7 indicates logic level
256*4882a593Smuzhiyun */
257*4882a593Smuzhiyun int gpio = (key & 0x7f) - 97;
258*4882a593Smuzhiyun int lvl = key & (1 << 7);
259*4882a593Smuzhiyun int bank = ADP5588_BANK(gpio);
260*4882a593Smuzhiyun int bit = ADP5588_BIT(gpio);
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun if ((lvl && dev->int_lvl_high[bank] & bit) ||
263*4882a593Smuzhiyun (!lvl && dev->int_lvl_low[bank] & bit))
264*4882a593Smuzhiyun handle_nested_irq(irq_find_mapping(
265*4882a593Smuzhiyun dev->gpio_chip.irq.domain, gpio));
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun }
268*4882a593Smuzhiyun }
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun adp5588_gpio_write(dev->client, INT_STAT, status); /* Status is W1C */
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun return IRQ_HANDLED;
273*4882a593Smuzhiyun }
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun
adp5588_irq_init_hw(struct gpio_chip * gc)276*4882a593Smuzhiyun static int adp5588_irq_init_hw(struct gpio_chip *gc)
277*4882a593Smuzhiyun {
278*4882a593Smuzhiyun struct adp5588_gpio *dev = gpiochip_get_data(gc);
279*4882a593Smuzhiyun /* Enable IRQs after registering chip */
280*4882a593Smuzhiyun adp5588_gpio_write(dev->client, CFG,
281*4882a593Smuzhiyun ADP5588_AUTO_INC | ADP5588_INT_CFG | ADP5588_KE_IEN);
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun return 0;
284*4882a593Smuzhiyun }
285*4882a593Smuzhiyun
adp5588_irq_setup(struct adp5588_gpio * dev)286*4882a593Smuzhiyun static int adp5588_irq_setup(struct adp5588_gpio *dev)
287*4882a593Smuzhiyun {
288*4882a593Smuzhiyun struct i2c_client *client = dev->client;
289*4882a593Smuzhiyun int ret;
290*4882a593Smuzhiyun struct adp5588_gpio_platform_data *pdata =
291*4882a593Smuzhiyun dev_get_platdata(&client->dev);
292*4882a593Smuzhiyun struct gpio_irq_chip *girq;
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun adp5588_gpio_write(client, CFG, ADP5588_AUTO_INC);
295*4882a593Smuzhiyun adp5588_gpio_write(client, INT_STAT, -1); /* status is W1C */
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun mutex_init(&dev->irq_lock);
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun ret = devm_request_threaded_irq(&client->dev, client->irq,
300*4882a593Smuzhiyun NULL, adp5588_irq_handler, IRQF_ONESHOT
301*4882a593Smuzhiyun | IRQF_TRIGGER_FALLING | IRQF_SHARED,
302*4882a593Smuzhiyun dev_name(&client->dev), dev);
303*4882a593Smuzhiyun if (ret) {
304*4882a593Smuzhiyun dev_err(&client->dev, "failed to request irq %d\n",
305*4882a593Smuzhiyun client->irq);
306*4882a593Smuzhiyun return ret;
307*4882a593Smuzhiyun }
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun /* This will be registered in the call to devm_gpiochip_add_data() */
310*4882a593Smuzhiyun girq = &dev->gpio_chip.irq;
311*4882a593Smuzhiyun girq->chip = &adp5588_irq_chip;
312*4882a593Smuzhiyun /* This will let us handle the parent IRQ in the driver */
313*4882a593Smuzhiyun girq->parent_handler = NULL;
314*4882a593Smuzhiyun girq->num_parents = 0;
315*4882a593Smuzhiyun girq->parents = NULL;
316*4882a593Smuzhiyun girq->first = pdata ? pdata->irq_base : 0;
317*4882a593Smuzhiyun girq->default_type = IRQ_TYPE_NONE;
318*4882a593Smuzhiyun girq->handler = handle_simple_irq;
319*4882a593Smuzhiyun girq->init_hw = adp5588_irq_init_hw;
320*4882a593Smuzhiyun girq->threaded = true;
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun return 0;
323*4882a593Smuzhiyun }
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun #else
adp5588_irq_setup(struct adp5588_gpio * dev)326*4882a593Smuzhiyun static int adp5588_irq_setup(struct adp5588_gpio *dev)
327*4882a593Smuzhiyun {
328*4882a593Smuzhiyun struct i2c_client *client = dev->client;
329*4882a593Smuzhiyun dev_warn(&client->dev, "interrupt support not compiled in\n");
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun return 0;
332*4882a593Smuzhiyun }
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun #endif /* CONFIG_GPIO_ADP5588_IRQ */
335*4882a593Smuzhiyun
adp5588_gpio_probe(struct i2c_client * client)336*4882a593Smuzhiyun static int adp5588_gpio_probe(struct i2c_client *client)
337*4882a593Smuzhiyun {
338*4882a593Smuzhiyun struct adp5588_gpio_platform_data *pdata =
339*4882a593Smuzhiyun dev_get_platdata(&client->dev);
340*4882a593Smuzhiyun struct adp5588_gpio *dev;
341*4882a593Smuzhiyun struct gpio_chip *gc;
342*4882a593Smuzhiyun int ret, i, revid;
343*4882a593Smuzhiyun unsigned int pullup_dis_mask = 0;
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun if (!i2c_check_functionality(client->adapter,
346*4882a593Smuzhiyun I2C_FUNC_SMBUS_BYTE_DATA)) {
347*4882a593Smuzhiyun dev_err(&client->dev, "SMBUS Byte Data not Supported\n");
348*4882a593Smuzhiyun return -EIO;
349*4882a593Smuzhiyun }
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun dev = devm_kzalloc(&client->dev, sizeof(*dev), GFP_KERNEL);
352*4882a593Smuzhiyun if (!dev)
353*4882a593Smuzhiyun return -ENOMEM;
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun dev->client = client;
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun gc = &dev->gpio_chip;
358*4882a593Smuzhiyun gc->direction_input = adp5588_gpio_direction_input;
359*4882a593Smuzhiyun gc->direction_output = adp5588_gpio_direction_output;
360*4882a593Smuzhiyun gc->get = adp5588_gpio_get_value;
361*4882a593Smuzhiyun gc->set = adp5588_gpio_set_value;
362*4882a593Smuzhiyun gc->can_sleep = true;
363*4882a593Smuzhiyun gc->base = -1;
364*4882a593Smuzhiyun gc->parent = &client->dev;
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun if (pdata) {
367*4882a593Smuzhiyun gc->base = pdata->gpio_start;
368*4882a593Smuzhiyun gc->names = pdata->names;
369*4882a593Smuzhiyun pullup_dis_mask = pdata->pullup_dis_mask;
370*4882a593Smuzhiyun }
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun gc->ngpio = ADP5588_MAXGPIO;
373*4882a593Smuzhiyun gc->label = client->name;
374*4882a593Smuzhiyun gc->owner = THIS_MODULE;
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun mutex_init(&dev->lock);
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun ret = adp5588_gpio_read(dev->client, DEV_ID);
379*4882a593Smuzhiyun if (ret < 0)
380*4882a593Smuzhiyun return ret;
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun revid = ret & ADP5588_DEVICE_ID_MASK;
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun for (i = 0, ret = 0; i <= ADP5588_BANK(ADP5588_MAXGPIO); i++) {
385*4882a593Smuzhiyun dev->dat_out[i] = adp5588_gpio_read(client, GPIO_DAT_OUT1 + i);
386*4882a593Smuzhiyun dev->dir[i] = adp5588_gpio_read(client, GPIO_DIR1 + i);
387*4882a593Smuzhiyun ret |= adp5588_gpio_write(client, KP_GPIO1 + i, 0);
388*4882a593Smuzhiyun ret |= adp5588_gpio_write(client, GPIO_PULL1 + i,
389*4882a593Smuzhiyun (pullup_dis_mask >> (8 * i)) & 0xFF);
390*4882a593Smuzhiyun ret |= adp5588_gpio_write(client, GPIO_INT_EN1 + i, 0);
391*4882a593Smuzhiyun if (ret)
392*4882a593Smuzhiyun return ret;
393*4882a593Smuzhiyun }
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun if (client->irq) {
396*4882a593Smuzhiyun if (WA_DELAYED_READOUT_REVID(revid)) {
397*4882a593Smuzhiyun dev_warn(&client->dev, "GPIO int not supported\n");
398*4882a593Smuzhiyun } else {
399*4882a593Smuzhiyun ret = adp5588_irq_setup(dev);
400*4882a593Smuzhiyun if (ret)
401*4882a593Smuzhiyun return ret;
402*4882a593Smuzhiyun }
403*4882a593Smuzhiyun }
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun ret = devm_gpiochip_add_data(&client->dev, &dev->gpio_chip, dev);
406*4882a593Smuzhiyun if (ret)
407*4882a593Smuzhiyun return ret;
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun if (pdata && pdata->setup) {
410*4882a593Smuzhiyun ret = pdata->setup(client, gc->base, gc->ngpio, pdata->context);
411*4882a593Smuzhiyun if (ret < 0)
412*4882a593Smuzhiyun dev_warn(&client->dev, "setup failed, %d\n", ret);
413*4882a593Smuzhiyun }
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun i2c_set_clientdata(client, dev);
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun return 0;
418*4882a593Smuzhiyun }
419*4882a593Smuzhiyun
adp5588_gpio_remove(struct i2c_client * client)420*4882a593Smuzhiyun static int adp5588_gpio_remove(struct i2c_client *client)
421*4882a593Smuzhiyun {
422*4882a593Smuzhiyun struct adp5588_gpio_platform_data *pdata =
423*4882a593Smuzhiyun dev_get_platdata(&client->dev);
424*4882a593Smuzhiyun struct adp5588_gpio *dev = i2c_get_clientdata(client);
425*4882a593Smuzhiyun int ret;
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun if (pdata && pdata->teardown) {
428*4882a593Smuzhiyun ret = pdata->teardown(client,
429*4882a593Smuzhiyun dev->gpio_chip.base, dev->gpio_chip.ngpio,
430*4882a593Smuzhiyun pdata->context);
431*4882a593Smuzhiyun if (ret < 0) {
432*4882a593Smuzhiyun dev_err(&client->dev, "teardown failed %d\n", ret);
433*4882a593Smuzhiyun return ret;
434*4882a593Smuzhiyun }
435*4882a593Smuzhiyun }
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun if (dev->client->irq)
438*4882a593Smuzhiyun free_irq(dev->client->irq, dev);
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun return 0;
441*4882a593Smuzhiyun }
442*4882a593Smuzhiyun
443*4882a593Smuzhiyun static const struct i2c_device_id adp5588_gpio_id[] = {
444*4882a593Smuzhiyun {DRV_NAME, 0},
445*4882a593Smuzhiyun {}
446*4882a593Smuzhiyun };
447*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, adp5588_gpio_id);
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun #ifdef CONFIG_OF
450*4882a593Smuzhiyun static const struct of_device_id adp5588_gpio_of_id[] = {
451*4882a593Smuzhiyun { .compatible = "adi," DRV_NAME, },
452*4882a593Smuzhiyun {},
453*4882a593Smuzhiyun };
454*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, adp5588_gpio_of_id);
455*4882a593Smuzhiyun #endif
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun static struct i2c_driver adp5588_gpio_driver = {
458*4882a593Smuzhiyun .driver = {
459*4882a593Smuzhiyun .name = DRV_NAME,
460*4882a593Smuzhiyun .of_match_table = of_match_ptr(adp5588_gpio_of_id),
461*4882a593Smuzhiyun },
462*4882a593Smuzhiyun .probe_new = adp5588_gpio_probe,
463*4882a593Smuzhiyun .remove = adp5588_gpio_remove,
464*4882a593Smuzhiyun .id_table = adp5588_gpio_id,
465*4882a593Smuzhiyun };
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun module_i2c_driver(adp5588_gpio_driver);
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
470*4882a593Smuzhiyun MODULE_DESCRIPTION("GPIO ADP5588 Driver");
471*4882a593Smuzhiyun MODULE_LICENSE("GPL");
472