1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * GPIO driver for the ACCES 104-IDIO-16 family
4*4882a593Smuzhiyun * Copyright (C) 2015 William Breathitt Gray
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * This driver supports the following ACCES devices: 104-IDIO-16,
7*4882a593Smuzhiyun * 104-IDIO-16E, 104-IDO-16, 104-IDIO-8, 104-IDIO-8E, and 104-IDO-8.
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun #include <linux/bitops.h>
10*4882a593Smuzhiyun #include <linux/device.h>
11*4882a593Smuzhiyun #include <linux/errno.h>
12*4882a593Smuzhiyun #include <linux/gpio/driver.h>
13*4882a593Smuzhiyun #include <linux/io.h>
14*4882a593Smuzhiyun #include <linux/ioport.h>
15*4882a593Smuzhiyun #include <linux/interrupt.h>
16*4882a593Smuzhiyun #include <linux/irqdesc.h>
17*4882a593Smuzhiyun #include <linux/isa.h>
18*4882a593Smuzhiyun #include <linux/kernel.h>
19*4882a593Smuzhiyun #include <linux/module.h>
20*4882a593Smuzhiyun #include <linux/moduleparam.h>
21*4882a593Smuzhiyun #include <linux/spinlock.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define IDIO_16_EXTENT 8
24*4882a593Smuzhiyun #define MAX_NUM_IDIO_16 max_num_isa_dev(IDIO_16_EXTENT)
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun static unsigned int base[MAX_NUM_IDIO_16];
27*4882a593Smuzhiyun static unsigned int num_idio_16;
28*4882a593Smuzhiyun module_param_hw_array(base, uint, ioport, &num_idio_16, 0);
29*4882a593Smuzhiyun MODULE_PARM_DESC(base, "ACCES 104-IDIO-16 base addresses");
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun static unsigned int irq[MAX_NUM_IDIO_16];
32*4882a593Smuzhiyun module_param_hw_array(irq, uint, irq, NULL, 0);
33*4882a593Smuzhiyun MODULE_PARM_DESC(irq, "ACCES 104-IDIO-16 interrupt line numbers");
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /**
36*4882a593Smuzhiyun * struct idio_16_gpio - GPIO device private data structure
37*4882a593Smuzhiyun * @chip: instance of the gpio_chip
38*4882a593Smuzhiyun * @lock: synchronization lock to prevent I/O race conditions
39*4882a593Smuzhiyun * @irq_mask: I/O bits affected by interrupts
40*4882a593Smuzhiyun * @base: base port address of the GPIO device
41*4882a593Smuzhiyun * @out_state: output bits state
42*4882a593Smuzhiyun */
43*4882a593Smuzhiyun struct idio_16_gpio {
44*4882a593Smuzhiyun struct gpio_chip chip;
45*4882a593Smuzhiyun raw_spinlock_t lock;
46*4882a593Smuzhiyun unsigned long irq_mask;
47*4882a593Smuzhiyun unsigned base;
48*4882a593Smuzhiyun unsigned out_state;
49*4882a593Smuzhiyun };
50*4882a593Smuzhiyun
idio_16_gpio_get_direction(struct gpio_chip * chip,unsigned offset)51*4882a593Smuzhiyun static int idio_16_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun if (offset > 15)
54*4882a593Smuzhiyun return GPIO_LINE_DIRECTION_IN;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun return GPIO_LINE_DIRECTION_OUT;
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
idio_16_gpio_direction_input(struct gpio_chip * chip,unsigned offset)59*4882a593Smuzhiyun static int idio_16_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun return 0;
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
idio_16_gpio_direction_output(struct gpio_chip * chip,unsigned offset,int value)64*4882a593Smuzhiyun static int idio_16_gpio_direction_output(struct gpio_chip *chip,
65*4882a593Smuzhiyun unsigned offset, int value)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun chip->set(chip, offset, value);
68*4882a593Smuzhiyun return 0;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
idio_16_gpio_get(struct gpio_chip * chip,unsigned offset)71*4882a593Smuzhiyun static int idio_16_gpio_get(struct gpio_chip *chip, unsigned offset)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
74*4882a593Smuzhiyun const unsigned mask = BIT(offset-16);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun if (offset < 16)
77*4882a593Smuzhiyun return -EINVAL;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun if (offset < 24)
80*4882a593Smuzhiyun return !!(inb(idio16gpio->base + 1) & mask);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun return !!(inb(idio16gpio->base + 5) & (mask>>8));
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
idio_16_gpio_get_multiple(struct gpio_chip * chip,unsigned long * mask,unsigned long * bits)85*4882a593Smuzhiyun static int idio_16_gpio_get_multiple(struct gpio_chip *chip,
86*4882a593Smuzhiyun unsigned long *mask, unsigned long *bits)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun *bits = 0;
91*4882a593Smuzhiyun if (*mask & GENMASK(23, 16))
92*4882a593Smuzhiyun *bits |= (unsigned long)inb(idio16gpio->base + 1) << 16;
93*4882a593Smuzhiyun if (*mask & GENMASK(31, 24))
94*4882a593Smuzhiyun *bits |= (unsigned long)inb(idio16gpio->base + 5) << 24;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun return 0;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
idio_16_gpio_set(struct gpio_chip * chip,unsigned offset,int value)99*4882a593Smuzhiyun static void idio_16_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
102*4882a593Smuzhiyun const unsigned mask = BIT(offset);
103*4882a593Smuzhiyun unsigned long flags;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun if (offset > 15)
106*4882a593Smuzhiyun return;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun raw_spin_lock_irqsave(&idio16gpio->lock, flags);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun if (value)
111*4882a593Smuzhiyun idio16gpio->out_state |= mask;
112*4882a593Smuzhiyun else
113*4882a593Smuzhiyun idio16gpio->out_state &= ~mask;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun if (offset > 7)
116*4882a593Smuzhiyun outb(idio16gpio->out_state >> 8, idio16gpio->base + 4);
117*4882a593Smuzhiyun else
118*4882a593Smuzhiyun outb(idio16gpio->out_state, idio16gpio->base);
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun
idio_16_gpio_set_multiple(struct gpio_chip * chip,unsigned long * mask,unsigned long * bits)123*4882a593Smuzhiyun static void idio_16_gpio_set_multiple(struct gpio_chip *chip,
124*4882a593Smuzhiyun unsigned long *mask, unsigned long *bits)
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
127*4882a593Smuzhiyun unsigned long flags;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun raw_spin_lock_irqsave(&idio16gpio->lock, flags);
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun idio16gpio->out_state &= ~*mask;
132*4882a593Smuzhiyun idio16gpio->out_state |= *mask & *bits;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun if (*mask & 0xFF)
135*4882a593Smuzhiyun outb(idio16gpio->out_state, idio16gpio->base);
136*4882a593Smuzhiyun if ((*mask >> 8) & 0xFF)
137*4882a593Smuzhiyun outb(idio16gpio->out_state >> 8, idio16gpio->base + 4);
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun
idio_16_irq_ack(struct irq_data * data)142*4882a593Smuzhiyun static void idio_16_irq_ack(struct irq_data *data)
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun
idio_16_irq_mask(struct irq_data * data)146*4882a593Smuzhiyun static void idio_16_irq_mask(struct irq_data *data)
147*4882a593Smuzhiyun {
148*4882a593Smuzhiyun struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
149*4882a593Smuzhiyun struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
150*4882a593Smuzhiyun const unsigned long mask = BIT(irqd_to_hwirq(data));
151*4882a593Smuzhiyun unsigned long flags;
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun idio16gpio->irq_mask &= ~mask;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun if (!idio16gpio->irq_mask) {
156*4882a593Smuzhiyun raw_spin_lock_irqsave(&idio16gpio->lock, flags);
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun outb(0, idio16gpio->base + 2);
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun
idio_16_irq_unmask(struct irq_data * data)164*4882a593Smuzhiyun static void idio_16_irq_unmask(struct irq_data *data)
165*4882a593Smuzhiyun {
166*4882a593Smuzhiyun struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
167*4882a593Smuzhiyun struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
168*4882a593Smuzhiyun const unsigned long mask = BIT(irqd_to_hwirq(data));
169*4882a593Smuzhiyun const unsigned long prev_irq_mask = idio16gpio->irq_mask;
170*4882a593Smuzhiyun unsigned long flags;
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun idio16gpio->irq_mask |= mask;
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun if (!prev_irq_mask) {
175*4882a593Smuzhiyun raw_spin_lock_irqsave(&idio16gpio->lock, flags);
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun inb(idio16gpio->base + 2);
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
180*4882a593Smuzhiyun }
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun
idio_16_irq_set_type(struct irq_data * data,unsigned flow_type)183*4882a593Smuzhiyun static int idio_16_irq_set_type(struct irq_data *data, unsigned flow_type)
184*4882a593Smuzhiyun {
185*4882a593Smuzhiyun /* The only valid irq types are none and both-edges */
186*4882a593Smuzhiyun if (flow_type != IRQ_TYPE_NONE &&
187*4882a593Smuzhiyun (flow_type & IRQ_TYPE_EDGE_BOTH) != IRQ_TYPE_EDGE_BOTH)
188*4882a593Smuzhiyun return -EINVAL;
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun return 0;
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun static struct irq_chip idio_16_irqchip = {
194*4882a593Smuzhiyun .name = "104-idio-16",
195*4882a593Smuzhiyun .irq_ack = idio_16_irq_ack,
196*4882a593Smuzhiyun .irq_mask = idio_16_irq_mask,
197*4882a593Smuzhiyun .irq_unmask = idio_16_irq_unmask,
198*4882a593Smuzhiyun .irq_set_type = idio_16_irq_set_type
199*4882a593Smuzhiyun };
200*4882a593Smuzhiyun
idio_16_irq_handler(int irq,void * dev_id)201*4882a593Smuzhiyun static irqreturn_t idio_16_irq_handler(int irq, void *dev_id)
202*4882a593Smuzhiyun {
203*4882a593Smuzhiyun struct idio_16_gpio *const idio16gpio = dev_id;
204*4882a593Smuzhiyun struct gpio_chip *const chip = &idio16gpio->chip;
205*4882a593Smuzhiyun int gpio;
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun for_each_set_bit(gpio, &idio16gpio->irq_mask, chip->ngpio)
208*4882a593Smuzhiyun generic_handle_irq(irq_find_mapping(chip->irq.domain, gpio));
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun raw_spin_lock(&idio16gpio->lock);
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun outb(0, idio16gpio->base + 1);
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun raw_spin_unlock(&idio16gpio->lock);
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun return IRQ_HANDLED;
217*4882a593Smuzhiyun }
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun #define IDIO_16_NGPIO 32
220*4882a593Smuzhiyun static const char *idio_16_names[IDIO_16_NGPIO] = {
221*4882a593Smuzhiyun "OUT0", "OUT1", "OUT2", "OUT3", "OUT4", "OUT5", "OUT6", "OUT7",
222*4882a593Smuzhiyun "OUT8", "OUT9", "OUT10", "OUT11", "OUT12", "OUT13", "OUT14", "OUT15",
223*4882a593Smuzhiyun "IIN0", "IIN1", "IIN2", "IIN3", "IIN4", "IIN5", "IIN6", "IIN7",
224*4882a593Smuzhiyun "IIN8", "IIN9", "IIN10", "IIN11", "IIN12", "IIN13", "IIN14", "IIN15"
225*4882a593Smuzhiyun };
226*4882a593Smuzhiyun
idio_16_irq_init_hw(struct gpio_chip * gc)227*4882a593Smuzhiyun static int idio_16_irq_init_hw(struct gpio_chip *gc)
228*4882a593Smuzhiyun {
229*4882a593Smuzhiyun struct idio_16_gpio *const idio16gpio = gpiochip_get_data(gc);
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun /* Disable IRQ by default */
232*4882a593Smuzhiyun outb(0, idio16gpio->base + 2);
233*4882a593Smuzhiyun outb(0, idio16gpio->base + 1);
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun return 0;
236*4882a593Smuzhiyun }
237*4882a593Smuzhiyun
idio_16_probe(struct device * dev,unsigned int id)238*4882a593Smuzhiyun static int idio_16_probe(struct device *dev, unsigned int id)
239*4882a593Smuzhiyun {
240*4882a593Smuzhiyun struct idio_16_gpio *idio16gpio;
241*4882a593Smuzhiyun const char *const name = dev_name(dev);
242*4882a593Smuzhiyun struct gpio_irq_chip *girq;
243*4882a593Smuzhiyun int err;
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun idio16gpio = devm_kzalloc(dev, sizeof(*idio16gpio), GFP_KERNEL);
246*4882a593Smuzhiyun if (!idio16gpio)
247*4882a593Smuzhiyun return -ENOMEM;
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun if (!devm_request_region(dev, base[id], IDIO_16_EXTENT, name)) {
250*4882a593Smuzhiyun dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
251*4882a593Smuzhiyun base[id], base[id] + IDIO_16_EXTENT);
252*4882a593Smuzhiyun return -EBUSY;
253*4882a593Smuzhiyun }
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun idio16gpio->chip.label = name;
256*4882a593Smuzhiyun idio16gpio->chip.parent = dev;
257*4882a593Smuzhiyun idio16gpio->chip.owner = THIS_MODULE;
258*4882a593Smuzhiyun idio16gpio->chip.base = -1;
259*4882a593Smuzhiyun idio16gpio->chip.ngpio = IDIO_16_NGPIO;
260*4882a593Smuzhiyun idio16gpio->chip.names = idio_16_names;
261*4882a593Smuzhiyun idio16gpio->chip.get_direction = idio_16_gpio_get_direction;
262*4882a593Smuzhiyun idio16gpio->chip.direction_input = idio_16_gpio_direction_input;
263*4882a593Smuzhiyun idio16gpio->chip.direction_output = idio_16_gpio_direction_output;
264*4882a593Smuzhiyun idio16gpio->chip.get = idio_16_gpio_get;
265*4882a593Smuzhiyun idio16gpio->chip.get_multiple = idio_16_gpio_get_multiple;
266*4882a593Smuzhiyun idio16gpio->chip.set = idio_16_gpio_set;
267*4882a593Smuzhiyun idio16gpio->chip.set_multiple = idio_16_gpio_set_multiple;
268*4882a593Smuzhiyun idio16gpio->base = base[id];
269*4882a593Smuzhiyun idio16gpio->out_state = 0xFFFF;
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun girq = &idio16gpio->chip.irq;
272*4882a593Smuzhiyun girq->chip = &idio_16_irqchip;
273*4882a593Smuzhiyun /* This will let us handle the parent IRQ in the driver */
274*4882a593Smuzhiyun girq->parent_handler = NULL;
275*4882a593Smuzhiyun girq->num_parents = 0;
276*4882a593Smuzhiyun girq->parents = NULL;
277*4882a593Smuzhiyun girq->default_type = IRQ_TYPE_NONE;
278*4882a593Smuzhiyun girq->handler = handle_edge_irq;
279*4882a593Smuzhiyun girq->init_hw = idio_16_irq_init_hw;
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun raw_spin_lock_init(&idio16gpio->lock);
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun err = devm_gpiochip_add_data(dev, &idio16gpio->chip, idio16gpio);
284*4882a593Smuzhiyun if (err) {
285*4882a593Smuzhiyun dev_err(dev, "GPIO registering failed (%d)\n", err);
286*4882a593Smuzhiyun return err;
287*4882a593Smuzhiyun }
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun err = devm_request_irq(dev, irq[id], idio_16_irq_handler, 0, name,
290*4882a593Smuzhiyun idio16gpio);
291*4882a593Smuzhiyun if (err) {
292*4882a593Smuzhiyun dev_err(dev, "IRQ handler registering failed (%d)\n", err);
293*4882a593Smuzhiyun return err;
294*4882a593Smuzhiyun }
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun return 0;
297*4882a593Smuzhiyun }
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun static struct isa_driver idio_16_driver = {
300*4882a593Smuzhiyun .probe = idio_16_probe,
301*4882a593Smuzhiyun .driver = {
302*4882a593Smuzhiyun .name = "104-idio-16"
303*4882a593Smuzhiyun },
304*4882a593Smuzhiyun };
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun module_isa_driver(idio_16_driver, num_idio_16);
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
309*4882a593Smuzhiyun MODULE_DESCRIPTION("ACCES 104-IDIO-16 GPIO driver");
310*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
311