1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * A FSI master controller, using a simple GPIO bit-banging interface
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/crc4.h>
7*4882a593Smuzhiyun #include <linux/delay.h>
8*4882a593Smuzhiyun #include <linux/device.h>
9*4882a593Smuzhiyun #include <linux/fsi.h>
10*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
11*4882a593Smuzhiyun #include <linux/io.h>
12*4882a593Smuzhiyun #include <linux/irqflags.h>
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/of.h>
15*4882a593Smuzhiyun #include <linux/platform_device.h>
16*4882a593Smuzhiyun #include <linux/slab.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include "fsi-master.h"
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define FSI_GPIO_STD_DLY 1 /* Standard pin delay in nS */
21*4882a593Smuzhiyun #define LAST_ADDR_INVALID 0x1
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun struct fsi_master_gpio {
24*4882a593Smuzhiyun struct fsi_master master;
25*4882a593Smuzhiyun struct device *dev;
26*4882a593Smuzhiyun struct mutex cmd_lock; /* mutex for command ordering */
27*4882a593Smuzhiyun struct gpio_desc *gpio_clk;
28*4882a593Smuzhiyun struct gpio_desc *gpio_data;
29*4882a593Smuzhiyun struct gpio_desc *gpio_trans; /* Voltage translator */
30*4882a593Smuzhiyun struct gpio_desc *gpio_enable; /* FSI enable */
31*4882a593Smuzhiyun struct gpio_desc *gpio_mux; /* Mux control */
32*4882a593Smuzhiyun bool external_mode;
33*4882a593Smuzhiyun bool no_delays;
34*4882a593Smuzhiyun uint32_t last_addr;
35*4882a593Smuzhiyun uint8_t t_send_delay;
36*4882a593Smuzhiyun uint8_t t_echo_delay;
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #define CREATE_TRACE_POINTS
40*4882a593Smuzhiyun #include <trace/events/fsi_master_gpio.h>
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #define to_fsi_master_gpio(m) container_of(m, struct fsi_master_gpio, master)
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun struct fsi_gpio_msg {
45*4882a593Smuzhiyun uint64_t msg;
46*4882a593Smuzhiyun uint8_t bits;
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun
clock_toggle(struct fsi_master_gpio * master,int count)49*4882a593Smuzhiyun static void clock_toggle(struct fsi_master_gpio *master, int count)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun int i;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun for (i = 0; i < count; i++) {
54*4882a593Smuzhiyun if (!master->no_delays)
55*4882a593Smuzhiyun ndelay(FSI_GPIO_STD_DLY);
56*4882a593Smuzhiyun gpiod_set_value(master->gpio_clk, 0);
57*4882a593Smuzhiyun if (!master->no_delays)
58*4882a593Smuzhiyun ndelay(FSI_GPIO_STD_DLY);
59*4882a593Smuzhiyun gpiod_set_value(master->gpio_clk, 1);
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
sda_clock_in(struct fsi_master_gpio * master)63*4882a593Smuzhiyun static int sda_clock_in(struct fsi_master_gpio *master)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun int in;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun if (!master->no_delays)
68*4882a593Smuzhiyun ndelay(FSI_GPIO_STD_DLY);
69*4882a593Smuzhiyun gpiod_set_value(master->gpio_clk, 0);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun /* Dummy read to feed the synchronizers */
72*4882a593Smuzhiyun gpiod_get_value(master->gpio_data);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /* Actual data read */
75*4882a593Smuzhiyun in = gpiod_get_value(master->gpio_data);
76*4882a593Smuzhiyun if (!master->no_delays)
77*4882a593Smuzhiyun ndelay(FSI_GPIO_STD_DLY);
78*4882a593Smuzhiyun gpiod_set_value(master->gpio_clk, 1);
79*4882a593Smuzhiyun return in ? 1 : 0;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
sda_out(struct fsi_master_gpio * master,int value)82*4882a593Smuzhiyun static void sda_out(struct fsi_master_gpio *master, int value)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun gpiod_set_value(master->gpio_data, value);
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
set_sda_input(struct fsi_master_gpio * master)87*4882a593Smuzhiyun static void set_sda_input(struct fsi_master_gpio *master)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun gpiod_direction_input(master->gpio_data);
90*4882a593Smuzhiyun gpiod_set_value(master->gpio_trans, 0);
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun
set_sda_output(struct fsi_master_gpio * master,int value)93*4882a593Smuzhiyun static void set_sda_output(struct fsi_master_gpio *master, int value)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun gpiod_set_value(master->gpio_trans, 1);
96*4882a593Smuzhiyun gpiod_direction_output(master->gpio_data, value);
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
clock_zeros(struct fsi_master_gpio * master,int count)99*4882a593Smuzhiyun static void clock_zeros(struct fsi_master_gpio *master, int count)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun trace_fsi_master_gpio_clock_zeros(master, count);
102*4882a593Smuzhiyun set_sda_output(master, 1);
103*4882a593Smuzhiyun clock_toggle(master, count);
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
echo_delay(struct fsi_master_gpio * master)106*4882a593Smuzhiyun static void echo_delay(struct fsi_master_gpio *master)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun clock_zeros(master, master->t_echo_delay);
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun
serial_in(struct fsi_master_gpio * master,struct fsi_gpio_msg * msg,uint8_t num_bits)112*4882a593Smuzhiyun static void serial_in(struct fsi_master_gpio *master, struct fsi_gpio_msg *msg,
113*4882a593Smuzhiyun uint8_t num_bits)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun uint8_t bit, in_bit;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun set_sda_input(master);
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun for (bit = 0; bit < num_bits; bit++) {
120*4882a593Smuzhiyun in_bit = sda_clock_in(master);
121*4882a593Smuzhiyun msg->msg <<= 1;
122*4882a593Smuzhiyun msg->msg |= ~in_bit & 0x1; /* Data is active low */
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun msg->bits += num_bits;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun trace_fsi_master_gpio_in(master, num_bits, msg->msg);
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun
serial_out(struct fsi_master_gpio * master,const struct fsi_gpio_msg * cmd)129*4882a593Smuzhiyun static void serial_out(struct fsi_master_gpio *master,
130*4882a593Smuzhiyun const struct fsi_gpio_msg *cmd)
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun uint8_t bit;
133*4882a593Smuzhiyun uint64_t msg = ~cmd->msg; /* Data is active low */
134*4882a593Smuzhiyun uint64_t sda_mask = 0x1ULL << (cmd->bits - 1);
135*4882a593Smuzhiyun uint64_t last_bit = ~0;
136*4882a593Smuzhiyun int next_bit;
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun trace_fsi_master_gpio_out(master, cmd->bits, cmd->msg);
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun if (!cmd->bits) {
141*4882a593Smuzhiyun dev_warn(master->dev, "trying to output 0 bits\n");
142*4882a593Smuzhiyun return;
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun set_sda_output(master, 0);
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun /* Send the start bit */
147*4882a593Smuzhiyun sda_out(master, 0);
148*4882a593Smuzhiyun clock_toggle(master, 1);
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun /* Send the message */
151*4882a593Smuzhiyun for (bit = 0; bit < cmd->bits; bit++) {
152*4882a593Smuzhiyun next_bit = (msg & sda_mask) >> (cmd->bits - 1);
153*4882a593Smuzhiyun if (last_bit ^ next_bit) {
154*4882a593Smuzhiyun sda_out(master, next_bit);
155*4882a593Smuzhiyun last_bit = next_bit;
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun clock_toggle(master, 1);
158*4882a593Smuzhiyun msg <<= 1;
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun
msg_push_bits(struct fsi_gpio_msg * msg,uint64_t data,int bits)162*4882a593Smuzhiyun static void msg_push_bits(struct fsi_gpio_msg *msg, uint64_t data, int bits)
163*4882a593Smuzhiyun {
164*4882a593Smuzhiyun msg->msg <<= bits;
165*4882a593Smuzhiyun msg->msg |= data & ((1ull << bits) - 1);
166*4882a593Smuzhiyun msg->bits += bits;
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun
msg_push_crc(struct fsi_gpio_msg * msg)169*4882a593Smuzhiyun static void msg_push_crc(struct fsi_gpio_msg *msg)
170*4882a593Smuzhiyun {
171*4882a593Smuzhiyun uint8_t crc;
172*4882a593Smuzhiyun int top;
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun top = msg->bits & 0x3;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun /* start bit, and any non-aligned top bits */
177*4882a593Smuzhiyun crc = crc4(0, 1 << top | msg->msg >> (msg->bits - top), top + 1);
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun /* aligned bits */
180*4882a593Smuzhiyun crc = crc4(crc, msg->msg, msg->bits - top);
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun msg_push_bits(msg, crc, 4);
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun
check_same_address(struct fsi_master_gpio * master,int id,uint32_t addr)185*4882a593Smuzhiyun static bool check_same_address(struct fsi_master_gpio *master, int id,
186*4882a593Smuzhiyun uint32_t addr)
187*4882a593Smuzhiyun {
188*4882a593Smuzhiyun /* this will also handle LAST_ADDR_INVALID */
189*4882a593Smuzhiyun return master->last_addr == (((id & 0x3) << 21) | (addr & ~0x3));
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun
check_relative_address(struct fsi_master_gpio * master,int id,uint32_t addr,uint32_t * rel_addrp)192*4882a593Smuzhiyun static bool check_relative_address(struct fsi_master_gpio *master, int id,
193*4882a593Smuzhiyun uint32_t addr, uint32_t *rel_addrp)
194*4882a593Smuzhiyun {
195*4882a593Smuzhiyun uint32_t last_addr = master->last_addr;
196*4882a593Smuzhiyun int32_t rel_addr;
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun if (last_addr == LAST_ADDR_INVALID)
199*4882a593Smuzhiyun return false;
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun /* We may be in 23-bit addressing mode, which uses the id as the
202*4882a593Smuzhiyun * top two address bits. So, if we're referencing a different ID,
203*4882a593Smuzhiyun * use absolute addresses.
204*4882a593Smuzhiyun */
205*4882a593Smuzhiyun if (((last_addr >> 21) & 0x3) != id)
206*4882a593Smuzhiyun return false;
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun /* remove the top two bits from any 23-bit addressing */
209*4882a593Smuzhiyun last_addr &= (1 << 21) - 1;
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun /* We know that the addresses are limited to 21 bits, so this won't
212*4882a593Smuzhiyun * overflow the signed rel_addr */
213*4882a593Smuzhiyun rel_addr = addr - last_addr;
214*4882a593Smuzhiyun if (rel_addr > 255 || rel_addr < -256)
215*4882a593Smuzhiyun return false;
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun *rel_addrp = (uint32_t)rel_addr;
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun return true;
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun
last_address_update(struct fsi_master_gpio * master,int id,bool valid,uint32_t addr)222*4882a593Smuzhiyun static void last_address_update(struct fsi_master_gpio *master,
223*4882a593Smuzhiyun int id, bool valid, uint32_t addr)
224*4882a593Smuzhiyun {
225*4882a593Smuzhiyun if (!valid)
226*4882a593Smuzhiyun master->last_addr = LAST_ADDR_INVALID;
227*4882a593Smuzhiyun else
228*4882a593Smuzhiyun master->last_addr = ((id & 0x3) << 21) | (addr & ~0x3);
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun /*
232*4882a593Smuzhiyun * Encode an Absolute/Relative/Same Address command
233*4882a593Smuzhiyun */
build_ar_command(struct fsi_master_gpio * master,struct fsi_gpio_msg * cmd,uint8_t id,uint32_t addr,size_t size,const void * data)234*4882a593Smuzhiyun static void build_ar_command(struct fsi_master_gpio *master,
235*4882a593Smuzhiyun struct fsi_gpio_msg *cmd, uint8_t id,
236*4882a593Smuzhiyun uint32_t addr, size_t size, const void *data)
237*4882a593Smuzhiyun {
238*4882a593Smuzhiyun int i, addr_bits, opcode_bits;
239*4882a593Smuzhiyun bool write = !!data;
240*4882a593Smuzhiyun uint8_t ds, opcode;
241*4882a593Smuzhiyun uint32_t rel_addr;
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun cmd->bits = 0;
244*4882a593Smuzhiyun cmd->msg = 0;
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun /* we have 21 bits of address max */
247*4882a593Smuzhiyun addr &= ((1 << 21) - 1);
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun /* cmd opcodes are variable length - SAME_AR is only two bits */
250*4882a593Smuzhiyun opcode_bits = 3;
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun if (check_same_address(master, id, addr)) {
253*4882a593Smuzhiyun /* we still address the byte offset within the word */
254*4882a593Smuzhiyun addr_bits = 2;
255*4882a593Smuzhiyun opcode_bits = 2;
256*4882a593Smuzhiyun opcode = FSI_CMD_SAME_AR;
257*4882a593Smuzhiyun trace_fsi_master_gpio_cmd_same_addr(master);
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun } else if (check_relative_address(master, id, addr, &rel_addr)) {
260*4882a593Smuzhiyun /* 8 bits plus sign */
261*4882a593Smuzhiyun addr_bits = 9;
262*4882a593Smuzhiyun addr = rel_addr;
263*4882a593Smuzhiyun opcode = FSI_CMD_REL_AR;
264*4882a593Smuzhiyun trace_fsi_master_gpio_cmd_rel_addr(master, rel_addr);
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun } else {
267*4882a593Smuzhiyun addr_bits = 21;
268*4882a593Smuzhiyun opcode = FSI_CMD_ABS_AR;
269*4882a593Smuzhiyun trace_fsi_master_gpio_cmd_abs_addr(master, addr);
270*4882a593Smuzhiyun }
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun /*
273*4882a593Smuzhiyun * The read/write size is encoded in the lower bits of the address
274*4882a593Smuzhiyun * (as it must be naturally-aligned), and the following ds bit.
275*4882a593Smuzhiyun *
276*4882a593Smuzhiyun * size addr:1 addr:0 ds
277*4882a593Smuzhiyun * 1 x x 0
278*4882a593Smuzhiyun * 2 x 0 1
279*4882a593Smuzhiyun * 4 0 1 1
280*4882a593Smuzhiyun *
281*4882a593Smuzhiyun */
282*4882a593Smuzhiyun ds = size > 1 ? 1 : 0;
283*4882a593Smuzhiyun addr &= ~(size - 1);
284*4882a593Smuzhiyun if (size == 4)
285*4882a593Smuzhiyun addr |= 1;
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun msg_push_bits(cmd, id, 2);
288*4882a593Smuzhiyun msg_push_bits(cmd, opcode, opcode_bits);
289*4882a593Smuzhiyun msg_push_bits(cmd, write ? 0 : 1, 1);
290*4882a593Smuzhiyun msg_push_bits(cmd, addr, addr_bits);
291*4882a593Smuzhiyun msg_push_bits(cmd, ds, 1);
292*4882a593Smuzhiyun for (i = 0; write && i < size; i++)
293*4882a593Smuzhiyun msg_push_bits(cmd, ((uint8_t *)data)[i], 8);
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun msg_push_crc(cmd);
296*4882a593Smuzhiyun }
297*4882a593Smuzhiyun
build_dpoll_command(struct fsi_gpio_msg * cmd,uint8_t slave_id)298*4882a593Smuzhiyun static void build_dpoll_command(struct fsi_gpio_msg *cmd, uint8_t slave_id)
299*4882a593Smuzhiyun {
300*4882a593Smuzhiyun cmd->bits = 0;
301*4882a593Smuzhiyun cmd->msg = 0;
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun msg_push_bits(cmd, slave_id, 2);
304*4882a593Smuzhiyun msg_push_bits(cmd, FSI_CMD_DPOLL, 3);
305*4882a593Smuzhiyun msg_push_crc(cmd);
306*4882a593Smuzhiyun }
307*4882a593Smuzhiyun
build_epoll_command(struct fsi_gpio_msg * cmd,uint8_t slave_id)308*4882a593Smuzhiyun static void build_epoll_command(struct fsi_gpio_msg *cmd, uint8_t slave_id)
309*4882a593Smuzhiyun {
310*4882a593Smuzhiyun cmd->bits = 0;
311*4882a593Smuzhiyun cmd->msg = 0;
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun msg_push_bits(cmd, slave_id, 2);
314*4882a593Smuzhiyun msg_push_bits(cmd, FSI_CMD_EPOLL, 3);
315*4882a593Smuzhiyun msg_push_crc(cmd);
316*4882a593Smuzhiyun }
317*4882a593Smuzhiyun
build_term_command(struct fsi_gpio_msg * cmd,uint8_t slave_id)318*4882a593Smuzhiyun static void build_term_command(struct fsi_gpio_msg *cmd, uint8_t slave_id)
319*4882a593Smuzhiyun {
320*4882a593Smuzhiyun cmd->bits = 0;
321*4882a593Smuzhiyun cmd->msg = 0;
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun msg_push_bits(cmd, slave_id, 2);
324*4882a593Smuzhiyun msg_push_bits(cmd, FSI_CMD_TERM, 6);
325*4882a593Smuzhiyun msg_push_crc(cmd);
326*4882a593Smuzhiyun }
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun /*
329*4882a593Smuzhiyun * Note: callers rely specifically on this returning -EAGAIN for
330*4882a593Smuzhiyun * a CRC error detected in the response. Use other error code
331*4882a593Smuzhiyun * for other situations. It will be converted to something else
332*4882a593Smuzhiyun * higher up the stack before it reaches userspace.
333*4882a593Smuzhiyun */
read_one_response(struct fsi_master_gpio * master,uint8_t data_size,struct fsi_gpio_msg * msgp,uint8_t * tagp)334*4882a593Smuzhiyun static int read_one_response(struct fsi_master_gpio *master,
335*4882a593Smuzhiyun uint8_t data_size, struct fsi_gpio_msg *msgp, uint8_t *tagp)
336*4882a593Smuzhiyun {
337*4882a593Smuzhiyun struct fsi_gpio_msg msg;
338*4882a593Smuzhiyun unsigned long flags;
339*4882a593Smuzhiyun uint32_t crc;
340*4882a593Smuzhiyun uint8_t tag;
341*4882a593Smuzhiyun int i;
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun local_irq_save(flags);
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun /* wait for the start bit */
346*4882a593Smuzhiyun for (i = 0; i < FSI_MASTER_MTOE_COUNT; i++) {
347*4882a593Smuzhiyun msg.bits = 0;
348*4882a593Smuzhiyun msg.msg = 0;
349*4882a593Smuzhiyun serial_in(master, &msg, 1);
350*4882a593Smuzhiyun if (msg.msg)
351*4882a593Smuzhiyun break;
352*4882a593Smuzhiyun }
353*4882a593Smuzhiyun if (i == FSI_MASTER_MTOE_COUNT) {
354*4882a593Smuzhiyun dev_dbg(master->dev,
355*4882a593Smuzhiyun "Master time out waiting for response\n");
356*4882a593Smuzhiyun local_irq_restore(flags);
357*4882a593Smuzhiyun return -ETIMEDOUT;
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun msg.bits = 0;
361*4882a593Smuzhiyun msg.msg = 0;
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun /* Read slave ID & response tag */
364*4882a593Smuzhiyun serial_in(master, &msg, 4);
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun tag = msg.msg & 0x3;
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun /* If we have an ACK and we're expecting data, clock the data in too */
369*4882a593Smuzhiyun if (tag == FSI_RESP_ACK && data_size)
370*4882a593Smuzhiyun serial_in(master, &msg, data_size * 8);
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun /* read CRC */
373*4882a593Smuzhiyun serial_in(master, &msg, FSI_CRC_SIZE);
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun local_irq_restore(flags);
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun /* we have a whole message now; check CRC */
378*4882a593Smuzhiyun crc = crc4(0, 1, 1);
379*4882a593Smuzhiyun crc = crc4(crc, msg.msg, msg.bits);
380*4882a593Smuzhiyun if (crc) {
381*4882a593Smuzhiyun /* Check if it's all 1's, that probably means the host is off */
382*4882a593Smuzhiyun if (((~msg.msg) & ((1ull << msg.bits) - 1)) == 0)
383*4882a593Smuzhiyun return -ENODEV;
384*4882a593Smuzhiyun dev_dbg(master->dev, "ERR response CRC msg: 0x%016llx (%d bits)\n",
385*4882a593Smuzhiyun msg.msg, msg.bits);
386*4882a593Smuzhiyun return -EAGAIN;
387*4882a593Smuzhiyun }
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun if (msgp)
390*4882a593Smuzhiyun *msgp = msg;
391*4882a593Smuzhiyun if (tagp)
392*4882a593Smuzhiyun *tagp = tag;
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun return 0;
395*4882a593Smuzhiyun }
396*4882a593Smuzhiyun
issue_term(struct fsi_master_gpio * master,uint8_t slave)397*4882a593Smuzhiyun static int issue_term(struct fsi_master_gpio *master, uint8_t slave)
398*4882a593Smuzhiyun {
399*4882a593Smuzhiyun struct fsi_gpio_msg cmd;
400*4882a593Smuzhiyun unsigned long flags;
401*4882a593Smuzhiyun uint8_t tag;
402*4882a593Smuzhiyun int rc;
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun build_term_command(&cmd, slave);
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun local_irq_save(flags);
407*4882a593Smuzhiyun serial_out(master, &cmd);
408*4882a593Smuzhiyun echo_delay(master);
409*4882a593Smuzhiyun local_irq_restore(flags);
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun rc = read_one_response(master, 0, NULL, &tag);
412*4882a593Smuzhiyun if (rc < 0) {
413*4882a593Smuzhiyun dev_err(master->dev,
414*4882a593Smuzhiyun "TERM failed; lost communication with slave\n");
415*4882a593Smuzhiyun return -EIO;
416*4882a593Smuzhiyun } else if (tag != FSI_RESP_ACK) {
417*4882a593Smuzhiyun dev_err(master->dev, "TERM failed; response %d\n", tag);
418*4882a593Smuzhiyun return -EIO;
419*4882a593Smuzhiyun }
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun return 0;
422*4882a593Smuzhiyun }
423*4882a593Smuzhiyun
poll_for_response(struct fsi_master_gpio * master,uint8_t slave,uint8_t size,void * data)424*4882a593Smuzhiyun static int poll_for_response(struct fsi_master_gpio *master,
425*4882a593Smuzhiyun uint8_t slave, uint8_t size, void *data)
426*4882a593Smuzhiyun {
427*4882a593Smuzhiyun struct fsi_gpio_msg response, cmd;
428*4882a593Smuzhiyun int busy_count = 0, rc, i;
429*4882a593Smuzhiyun unsigned long flags;
430*4882a593Smuzhiyun uint8_t tag;
431*4882a593Smuzhiyun uint8_t *data_byte = data;
432*4882a593Smuzhiyun int crc_err_retries = 0;
433*4882a593Smuzhiyun retry:
434*4882a593Smuzhiyun rc = read_one_response(master, size, &response, &tag);
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun /* Handle retries on CRC errors */
437*4882a593Smuzhiyun if (rc == -EAGAIN) {
438*4882a593Smuzhiyun /* Too many retries ? */
439*4882a593Smuzhiyun if (crc_err_retries++ > FSI_CRC_ERR_RETRIES) {
440*4882a593Smuzhiyun /*
441*4882a593Smuzhiyun * Pass it up as a -EIO otherwise upper level will retry
442*4882a593Smuzhiyun * the whole command which isn't what we want here.
443*4882a593Smuzhiyun */
444*4882a593Smuzhiyun rc = -EIO;
445*4882a593Smuzhiyun goto fail;
446*4882a593Smuzhiyun }
447*4882a593Smuzhiyun dev_dbg(master->dev,
448*4882a593Smuzhiyun "CRC error retry %d\n", crc_err_retries);
449*4882a593Smuzhiyun trace_fsi_master_gpio_crc_rsp_error(master);
450*4882a593Smuzhiyun build_epoll_command(&cmd, slave);
451*4882a593Smuzhiyun local_irq_save(flags);
452*4882a593Smuzhiyun clock_zeros(master, FSI_MASTER_EPOLL_CLOCKS);
453*4882a593Smuzhiyun serial_out(master, &cmd);
454*4882a593Smuzhiyun echo_delay(master);
455*4882a593Smuzhiyun local_irq_restore(flags);
456*4882a593Smuzhiyun goto retry;
457*4882a593Smuzhiyun } else if (rc)
458*4882a593Smuzhiyun goto fail;
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun switch (tag) {
461*4882a593Smuzhiyun case FSI_RESP_ACK:
462*4882a593Smuzhiyun if (size && data) {
463*4882a593Smuzhiyun uint64_t val = response.msg;
464*4882a593Smuzhiyun /* clear crc & mask */
465*4882a593Smuzhiyun val >>= 4;
466*4882a593Smuzhiyun val &= (1ull << (size * 8)) - 1;
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun for (i = 0; i < size; i++) {
469*4882a593Smuzhiyun data_byte[size-i-1] = val;
470*4882a593Smuzhiyun val >>= 8;
471*4882a593Smuzhiyun }
472*4882a593Smuzhiyun }
473*4882a593Smuzhiyun break;
474*4882a593Smuzhiyun case FSI_RESP_BUSY:
475*4882a593Smuzhiyun /*
476*4882a593Smuzhiyun * Its necessary to clock slave before issuing
477*4882a593Smuzhiyun * d-poll, not indicated in the hardware protocol
478*4882a593Smuzhiyun * spec. < 20 clocks causes slave to hang, 21 ok.
479*4882a593Smuzhiyun */
480*4882a593Smuzhiyun if (busy_count++ < FSI_MASTER_MAX_BUSY) {
481*4882a593Smuzhiyun build_dpoll_command(&cmd, slave);
482*4882a593Smuzhiyun local_irq_save(flags);
483*4882a593Smuzhiyun clock_zeros(master, FSI_MASTER_DPOLL_CLOCKS);
484*4882a593Smuzhiyun serial_out(master, &cmd);
485*4882a593Smuzhiyun echo_delay(master);
486*4882a593Smuzhiyun local_irq_restore(flags);
487*4882a593Smuzhiyun goto retry;
488*4882a593Smuzhiyun }
489*4882a593Smuzhiyun dev_warn(master->dev,
490*4882a593Smuzhiyun "ERR slave is stuck in busy state, issuing TERM\n");
491*4882a593Smuzhiyun local_irq_save(flags);
492*4882a593Smuzhiyun clock_zeros(master, FSI_MASTER_DPOLL_CLOCKS);
493*4882a593Smuzhiyun local_irq_restore(flags);
494*4882a593Smuzhiyun issue_term(master, slave);
495*4882a593Smuzhiyun rc = -EIO;
496*4882a593Smuzhiyun break;
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun case FSI_RESP_ERRA:
499*4882a593Smuzhiyun dev_dbg(master->dev, "ERRA received: 0x%x\n", (int)response.msg);
500*4882a593Smuzhiyun rc = -EIO;
501*4882a593Smuzhiyun break;
502*4882a593Smuzhiyun case FSI_RESP_ERRC:
503*4882a593Smuzhiyun dev_dbg(master->dev, "ERRC received: 0x%x\n", (int)response.msg);
504*4882a593Smuzhiyun trace_fsi_master_gpio_crc_cmd_error(master);
505*4882a593Smuzhiyun rc = -EAGAIN;
506*4882a593Smuzhiyun break;
507*4882a593Smuzhiyun }
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun if (busy_count > 0)
510*4882a593Smuzhiyun trace_fsi_master_gpio_poll_response_busy(master, busy_count);
511*4882a593Smuzhiyun fail:
512*4882a593Smuzhiyun /*
513*4882a593Smuzhiyun * tSendDelay clocks, avoids signal reflections when switching
514*4882a593Smuzhiyun * from receive of response back to send of data.
515*4882a593Smuzhiyun */
516*4882a593Smuzhiyun local_irq_save(flags);
517*4882a593Smuzhiyun clock_zeros(master, master->t_send_delay);
518*4882a593Smuzhiyun local_irq_restore(flags);
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun return rc;
521*4882a593Smuzhiyun }
522*4882a593Smuzhiyun
send_request(struct fsi_master_gpio * master,struct fsi_gpio_msg * cmd)523*4882a593Smuzhiyun static int send_request(struct fsi_master_gpio *master,
524*4882a593Smuzhiyun struct fsi_gpio_msg *cmd)
525*4882a593Smuzhiyun {
526*4882a593Smuzhiyun unsigned long flags;
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun if (master->external_mode)
529*4882a593Smuzhiyun return -EBUSY;
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun local_irq_save(flags);
532*4882a593Smuzhiyun serial_out(master, cmd);
533*4882a593Smuzhiyun echo_delay(master);
534*4882a593Smuzhiyun local_irq_restore(flags);
535*4882a593Smuzhiyun
536*4882a593Smuzhiyun return 0;
537*4882a593Smuzhiyun }
538*4882a593Smuzhiyun
fsi_master_gpio_xfer(struct fsi_master_gpio * master,uint8_t slave,struct fsi_gpio_msg * cmd,size_t resp_len,void * resp)539*4882a593Smuzhiyun static int fsi_master_gpio_xfer(struct fsi_master_gpio *master, uint8_t slave,
540*4882a593Smuzhiyun struct fsi_gpio_msg *cmd, size_t resp_len, void *resp)
541*4882a593Smuzhiyun {
542*4882a593Smuzhiyun int rc = -EAGAIN, retries = 0;
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun while ((retries++) < FSI_CRC_ERR_RETRIES) {
545*4882a593Smuzhiyun rc = send_request(master, cmd);
546*4882a593Smuzhiyun if (rc)
547*4882a593Smuzhiyun break;
548*4882a593Smuzhiyun rc = poll_for_response(master, slave, resp_len, resp);
549*4882a593Smuzhiyun if (rc != -EAGAIN)
550*4882a593Smuzhiyun break;
551*4882a593Smuzhiyun rc = -EIO;
552*4882a593Smuzhiyun dev_warn(master->dev, "ECRC retry %d\n", retries);
553*4882a593Smuzhiyun
554*4882a593Smuzhiyun /* Pace it a bit before retry */
555*4882a593Smuzhiyun msleep(1);
556*4882a593Smuzhiyun }
557*4882a593Smuzhiyun
558*4882a593Smuzhiyun return rc;
559*4882a593Smuzhiyun }
560*4882a593Smuzhiyun
fsi_master_gpio_read(struct fsi_master * _master,int link,uint8_t id,uint32_t addr,void * val,size_t size)561*4882a593Smuzhiyun static int fsi_master_gpio_read(struct fsi_master *_master, int link,
562*4882a593Smuzhiyun uint8_t id, uint32_t addr, void *val, size_t size)
563*4882a593Smuzhiyun {
564*4882a593Smuzhiyun struct fsi_master_gpio *master = to_fsi_master_gpio(_master);
565*4882a593Smuzhiyun struct fsi_gpio_msg cmd;
566*4882a593Smuzhiyun int rc;
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun if (link != 0)
569*4882a593Smuzhiyun return -ENODEV;
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun mutex_lock(&master->cmd_lock);
572*4882a593Smuzhiyun build_ar_command(master, &cmd, id, addr, size, NULL);
573*4882a593Smuzhiyun rc = fsi_master_gpio_xfer(master, id, &cmd, size, val);
574*4882a593Smuzhiyun last_address_update(master, id, rc == 0, addr);
575*4882a593Smuzhiyun mutex_unlock(&master->cmd_lock);
576*4882a593Smuzhiyun
577*4882a593Smuzhiyun return rc;
578*4882a593Smuzhiyun }
579*4882a593Smuzhiyun
fsi_master_gpio_write(struct fsi_master * _master,int link,uint8_t id,uint32_t addr,const void * val,size_t size)580*4882a593Smuzhiyun static int fsi_master_gpio_write(struct fsi_master *_master, int link,
581*4882a593Smuzhiyun uint8_t id, uint32_t addr, const void *val, size_t size)
582*4882a593Smuzhiyun {
583*4882a593Smuzhiyun struct fsi_master_gpio *master = to_fsi_master_gpio(_master);
584*4882a593Smuzhiyun struct fsi_gpio_msg cmd;
585*4882a593Smuzhiyun int rc;
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun if (link != 0)
588*4882a593Smuzhiyun return -ENODEV;
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun mutex_lock(&master->cmd_lock);
591*4882a593Smuzhiyun build_ar_command(master, &cmd, id, addr, size, val);
592*4882a593Smuzhiyun rc = fsi_master_gpio_xfer(master, id, &cmd, 0, NULL);
593*4882a593Smuzhiyun last_address_update(master, id, rc == 0, addr);
594*4882a593Smuzhiyun mutex_unlock(&master->cmd_lock);
595*4882a593Smuzhiyun
596*4882a593Smuzhiyun return rc;
597*4882a593Smuzhiyun }
598*4882a593Smuzhiyun
fsi_master_gpio_term(struct fsi_master * _master,int link,uint8_t id)599*4882a593Smuzhiyun static int fsi_master_gpio_term(struct fsi_master *_master,
600*4882a593Smuzhiyun int link, uint8_t id)
601*4882a593Smuzhiyun {
602*4882a593Smuzhiyun struct fsi_master_gpio *master = to_fsi_master_gpio(_master);
603*4882a593Smuzhiyun struct fsi_gpio_msg cmd;
604*4882a593Smuzhiyun int rc;
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun if (link != 0)
607*4882a593Smuzhiyun return -ENODEV;
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun mutex_lock(&master->cmd_lock);
610*4882a593Smuzhiyun build_term_command(&cmd, id);
611*4882a593Smuzhiyun rc = fsi_master_gpio_xfer(master, id, &cmd, 0, NULL);
612*4882a593Smuzhiyun last_address_update(master, id, false, 0);
613*4882a593Smuzhiyun mutex_unlock(&master->cmd_lock);
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun return rc;
616*4882a593Smuzhiyun }
617*4882a593Smuzhiyun
fsi_master_gpio_break(struct fsi_master * _master,int link)618*4882a593Smuzhiyun static int fsi_master_gpio_break(struct fsi_master *_master, int link)
619*4882a593Smuzhiyun {
620*4882a593Smuzhiyun struct fsi_master_gpio *master = to_fsi_master_gpio(_master);
621*4882a593Smuzhiyun unsigned long flags;
622*4882a593Smuzhiyun
623*4882a593Smuzhiyun if (link != 0)
624*4882a593Smuzhiyun return -ENODEV;
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun trace_fsi_master_gpio_break(master);
627*4882a593Smuzhiyun
628*4882a593Smuzhiyun mutex_lock(&master->cmd_lock);
629*4882a593Smuzhiyun if (master->external_mode) {
630*4882a593Smuzhiyun mutex_unlock(&master->cmd_lock);
631*4882a593Smuzhiyun return -EBUSY;
632*4882a593Smuzhiyun }
633*4882a593Smuzhiyun
634*4882a593Smuzhiyun local_irq_save(flags);
635*4882a593Smuzhiyun
636*4882a593Smuzhiyun set_sda_output(master, 1);
637*4882a593Smuzhiyun sda_out(master, 1);
638*4882a593Smuzhiyun clock_toggle(master, FSI_PRE_BREAK_CLOCKS);
639*4882a593Smuzhiyun sda_out(master, 0);
640*4882a593Smuzhiyun clock_toggle(master, FSI_BREAK_CLOCKS);
641*4882a593Smuzhiyun echo_delay(master);
642*4882a593Smuzhiyun sda_out(master, 1);
643*4882a593Smuzhiyun clock_toggle(master, FSI_POST_BREAK_CLOCKS);
644*4882a593Smuzhiyun
645*4882a593Smuzhiyun local_irq_restore(flags);
646*4882a593Smuzhiyun
647*4882a593Smuzhiyun last_address_update(master, 0, false, 0);
648*4882a593Smuzhiyun mutex_unlock(&master->cmd_lock);
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun /* Wait for logic reset to take effect */
651*4882a593Smuzhiyun udelay(200);
652*4882a593Smuzhiyun
653*4882a593Smuzhiyun return 0;
654*4882a593Smuzhiyun }
655*4882a593Smuzhiyun
fsi_master_gpio_init(struct fsi_master_gpio * master)656*4882a593Smuzhiyun static void fsi_master_gpio_init(struct fsi_master_gpio *master)
657*4882a593Smuzhiyun {
658*4882a593Smuzhiyun unsigned long flags;
659*4882a593Smuzhiyun
660*4882a593Smuzhiyun gpiod_direction_output(master->gpio_mux, 1);
661*4882a593Smuzhiyun gpiod_direction_output(master->gpio_trans, 1);
662*4882a593Smuzhiyun gpiod_direction_output(master->gpio_enable, 1);
663*4882a593Smuzhiyun gpiod_direction_output(master->gpio_clk, 1);
664*4882a593Smuzhiyun gpiod_direction_output(master->gpio_data, 1);
665*4882a593Smuzhiyun
666*4882a593Smuzhiyun /* todo: evaluate if clocks can be reduced */
667*4882a593Smuzhiyun local_irq_save(flags);
668*4882a593Smuzhiyun clock_zeros(master, FSI_INIT_CLOCKS);
669*4882a593Smuzhiyun local_irq_restore(flags);
670*4882a593Smuzhiyun }
671*4882a593Smuzhiyun
fsi_master_gpio_init_external(struct fsi_master_gpio * master)672*4882a593Smuzhiyun static void fsi_master_gpio_init_external(struct fsi_master_gpio *master)
673*4882a593Smuzhiyun {
674*4882a593Smuzhiyun gpiod_direction_output(master->gpio_mux, 0);
675*4882a593Smuzhiyun gpiod_direction_output(master->gpio_trans, 0);
676*4882a593Smuzhiyun gpiod_direction_output(master->gpio_enable, 1);
677*4882a593Smuzhiyun gpiod_direction_input(master->gpio_clk);
678*4882a593Smuzhiyun gpiod_direction_input(master->gpio_data);
679*4882a593Smuzhiyun }
680*4882a593Smuzhiyun
fsi_master_gpio_link_enable(struct fsi_master * _master,int link,bool enable)681*4882a593Smuzhiyun static int fsi_master_gpio_link_enable(struct fsi_master *_master, int link,
682*4882a593Smuzhiyun bool enable)
683*4882a593Smuzhiyun {
684*4882a593Smuzhiyun struct fsi_master_gpio *master = to_fsi_master_gpio(_master);
685*4882a593Smuzhiyun int rc = -EBUSY;
686*4882a593Smuzhiyun
687*4882a593Smuzhiyun if (link != 0)
688*4882a593Smuzhiyun return -ENODEV;
689*4882a593Smuzhiyun
690*4882a593Smuzhiyun mutex_lock(&master->cmd_lock);
691*4882a593Smuzhiyun if (!master->external_mode) {
692*4882a593Smuzhiyun gpiod_set_value(master->gpio_enable, enable ? 1 : 0);
693*4882a593Smuzhiyun rc = 0;
694*4882a593Smuzhiyun }
695*4882a593Smuzhiyun mutex_unlock(&master->cmd_lock);
696*4882a593Smuzhiyun
697*4882a593Smuzhiyun return rc;
698*4882a593Smuzhiyun }
699*4882a593Smuzhiyun
fsi_master_gpio_link_config(struct fsi_master * _master,int link,u8 t_send_delay,u8 t_echo_delay)700*4882a593Smuzhiyun static int fsi_master_gpio_link_config(struct fsi_master *_master, int link,
701*4882a593Smuzhiyun u8 t_send_delay, u8 t_echo_delay)
702*4882a593Smuzhiyun {
703*4882a593Smuzhiyun struct fsi_master_gpio *master = to_fsi_master_gpio(_master);
704*4882a593Smuzhiyun
705*4882a593Smuzhiyun if (link != 0)
706*4882a593Smuzhiyun return -ENODEV;
707*4882a593Smuzhiyun
708*4882a593Smuzhiyun mutex_lock(&master->cmd_lock);
709*4882a593Smuzhiyun master->t_send_delay = t_send_delay;
710*4882a593Smuzhiyun master->t_echo_delay = t_echo_delay;
711*4882a593Smuzhiyun mutex_unlock(&master->cmd_lock);
712*4882a593Smuzhiyun
713*4882a593Smuzhiyun return 0;
714*4882a593Smuzhiyun }
715*4882a593Smuzhiyun
external_mode_show(struct device * dev,struct device_attribute * attr,char * buf)716*4882a593Smuzhiyun static ssize_t external_mode_show(struct device *dev,
717*4882a593Smuzhiyun struct device_attribute *attr, char *buf)
718*4882a593Smuzhiyun {
719*4882a593Smuzhiyun struct fsi_master_gpio *master = dev_get_drvdata(dev);
720*4882a593Smuzhiyun
721*4882a593Smuzhiyun return snprintf(buf, PAGE_SIZE - 1, "%u\n",
722*4882a593Smuzhiyun master->external_mode ? 1 : 0);
723*4882a593Smuzhiyun }
724*4882a593Smuzhiyun
external_mode_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)725*4882a593Smuzhiyun static ssize_t external_mode_store(struct device *dev,
726*4882a593Smuzhiyun struct device_attribute *attr, const char *buf, size_t count)
727*4882a593Smuzhiyun {
728*4882a593Smuzhiyun struct fsi_master_gpio *master = dev_get_drvdata(dev);
729*4882a593Smuzhiyun unsigned long val;
730*4882a593Smuzhiyun bool external_mode;
731*4882a593Smuzhiyun int err;
732*4882a593Smuzhiyun
733*4882a593Smuzhiyun err = kstrtoul(buf, 0, &val);
734*4882a593Smuzhiyun if (err)
735*4882a593Smuzhiyun return err;
736*4882a593Smuzhiyun
737*4882a593Smuzhiyun external_mode = !!val;
738*4882a593Smuzhiyun
739*4882a593Smuzhiyun mutex_lock(&master->cmd_lock);
740*4882a593Smuzhiyun
741*4882a593Smuzhiyun if (external_mode == master->external_mode) {
742*4882a593Smuzhiyun mutex_unlock(&master->cmd_lock);
743*4882a593Smuzhiyun return count;
744*4882a593Smuzhiyun }
745*4882a593Smuzhiyun
746*4882a593Smuzhiyun master->external_mode = external_mode;
747*4882a593Smuzhiyun if (master->external_mode)
748*4882a593Smuzhiyun fsi_master_gpio_init_external(master);
749*4882a593Smuzhiyun else
750*4882a593Smuzhiyun fsi_master_gpio_init(master);
751*4882a593Smuzhiyun
752*4882a593Smuzhiyun mutex_unlock(&master->cmd_lock);
753*4882a593Smuzhiyun
754*4882a593Smuzhiyun fsi_master_rescan(&master->master);
755*4882a593Smuzhiyun
756*4882a593Smuzhiyun return count;
757*4882a593Smuzhiyun }
758*4882a593Smuzhiyun
759*4882a593Smuzhiyun static DEVICE_ATTR(external_mode, 0664,
760*4882a593Smuzhiyun external_mode_show, external_mode_store);
761*4882a593Smuzhiyun
fsi_master_gpio_release(struct device * dev)762*4882a593Smuzhiyun static void fsi_master_gpio_release(struct device *dev)
763*4882a593Smuzhiyun {
764*4882a593Smuzhiyun struct fsi_master_gpio *master = to_fsi_master_gpio(dev_to_fsi_master(dev));
765*4882a593Smuzhiyun
766*4882a593Smuzhiyun of_node_put(dev_of_node(master->dev));
767*4882a593Smuzhiyun
768*4882a593Smuzhiyun kfree(master);
769*4882a593Smuzhiyun }
770*4882a593Smuzhiyun
fsi_master_gpio_probe(struct platform_device * pdev)771*4882a593Smuzhiyun static int fsi_master_gpio_probe(struct platform_device *pdev)
772*4882a593Smuzhiyun {
773*4882a593Smuzhiyun struct fsi_master_gpio *master;
774*4882a593Smuzhiyun struct gpio_desc *gpio;
775*4882a593Smuzhiyun int rc;
776*4882a593Smuzhiyun
777*4882a593Smuzhiyun master = kzalloc(sizeof(*master), GFP_KERNEL);
778*4882a593Smuzhiyun if (!master)
779*4882a593Smuzhiyun return -ENOMEM;
780*4882a593Smuzhiyun
781*4882a593Smuzhiyun master->dev = &pdev->dev;
782*4882a593Smuzhiyun master->master.dev.parent = master->dev;
783*4882a593Smuzhiyun master->master.dev.of_node = of_node_get(dev_of_node(master->dev));
784*4882a593Smuzhiyun master->master.dev.release = fsi_master_gpio_release;
785*4882a593Smuzhiyun master->last_addr = LAST_ADDR_INVALID;
786*4882a593Smuzhiyun
787*4882a593Smuzhiyun gpio = devm_gpiod_get(&pdev->dev, "clock", 0);
788*4882a593Smuzhiyun if (IS_ERR(gpio)) {
789*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to get clock gpio\n");
790*4882a593Smuzhiyun rc = PTR_ERR(gpio);
791*4882a593Smuzhiyun goto err_free;
792*4882a593Smuzhiyun }
793*4882a593Smuzhiyun master->gpio_clk = gpio;
794*4882a593Smuzhiyun
795*4882a593Smuzhiyun gpio = devm_gpiod_get(&pdev->dev, "data", 0);
796*4882a593Smuzhiyun if (IS_ERR(gpio)) {
797*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to get data gpio\n");
798*4882a593Smuzhiyun rc = PTR_ERR(gpio);
799*4882a593Smuzhiyun goto err_free;
800*4882a593Smuzhiyun }
801*4882a593Smuzhiyun master->gpio_data = gpio;
802*4882a593Smuzhiyun
803*4882a593Smuzhiyun /* Optional GPIOs */
804*4882a593Smuzhiyun gpio = devm_gpiod_get_optional(&pdev->dev, "trans", 0);
805*4882a593Smuzhiyun if (IS_ERR(gpio)) {
806*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to get trans gpio\n");
807*4882a593Smuzhiyun rc = PTR_ERR(gpio);
808*4882a593Smuzhiyun goto err_free;
809*4882a593Smuzhiyun }
810*4882a593Smuzhiyun master->gpio_trans = gpio;
811*4882a593Smuzhiyun
812*4882a593Smuzhiyun gpio = devm_gpiod_get_optional(&pdev->dev, "enable", 0);
813*4882a593Smuzhiyun if (IS_ERR(gpio)) {
814*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to get enable gpio\n");
815*4882a593Smuzhiyun rc = PTR_ERR(gpio);
816*4882a593Smuzhiyun goto err_free;
817*4882a593Smuzhiyun }
818*4882a593Smuzhiyun master->gpio_enable = gpio;
819*4882a593Smuzhiyun
820*4882a593Smuzhiyun gpio = devm_gpiod_get_optional(&pdev->dev, "mux", 0);
821*4882a593Smuzhiyun if (IS_ERR(gpio)) {
822*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to get mux gpio\n");
823*4882a593Smuzhiyun rc = PTR_ERR(gpio);
824*4882a593Smuzhiyun goto err_free;
825*4882a593Smuzhiyun }
826*4882a593Smuzhiyun master->gpio_mux = gpio;
827*4882a593Smuzhiyun
828*4882a593Smuzhiyun /*
829*4882a593Smuzhiyun * Check if GPIO block is slow enought that no extra delays
830*4882a593Smuzhiyun * are necessary. This improves performance on ast2500 by
831*4882a593Smuzhiyun * an order of magnitude.
832*4882a593Smuzhiyun */
833*4882a593Smuzhiyun master->no_delays = device_property_present(&pdev->dev, "no-gpio-delays");
834*4882a593Smuzhiyun
835*4882a593Smuzhiyun /* Default FSI command delays */
836*4882a593Smuzhiyun master->t_send_delay = FSI_SEND_DELAY_CLOCKS;
837*4882a593Smuzhiyun master->t_echo_delay = FSI_ECHO_DELAY_CLOCKS;
838*4882a593Smuzhiyun
839*4882a593Smuzhiyun master->master.n_links = 1;
840*4882a593Smuzhiyun master->master.flags = FSI_MASTER_FLAG_SWCLOCK;
841*4882a593Smuzhiyun master->master.read = fsi_master_gpio_read;
842*4882a593Smuzhiyun master->master.write = fsi_master_gpio_write;
843*4882a593Smuzhiyun master->master.term = fsi_master_gpio_term;
844*4882a593Smuzhiyun master->master.send_break = fsi_master_gpio_break;
845*4882a593Smuzhiyun master->master.link_enable = fsi_master_gpio_link_enable;
846*4882a593Smuzhiyun master->master.link_config = fsi_master_gpio_link_config;
847*4882a593Smuzhiyun platform_set_drvdata(pdev, master);
848*4882a593Smuzhiyun mutex_init(&master->cmd_lock);
849*4882a593Smuzhiyun
850*4882a593Smuzhiyun fsi_master_gpio_init(master);
851*4882a593Smuzhiyun
852*4882a593Smuzhiyun rc = device_create_file(&pdev->dev, &dev_attr_external_mode);
853*4882a593Smuzhiyun if (rc)
854*4882a593Smuzhiyun goto err_free;
855*4882a593Smuzhiyun
856*4882a593Smuzhiyun rc = fsi_master_register(&master->master);
857*4882a593Smuzhiyun if (rc) {
858*4882a593Smuzhiyun device_remove_file(&pdev->dev, &dev_attr_external_mode);
859*4882a593Smuzhiyun put_device(&master->master.dev);
860*4882a593Smuzhiyun return rc;
861*4882a593Smuzhiyun }
862*4882a593Smuzhiyun return 0;
863*4882a593Smuzhiyun err_free:
864*4882a593Smuzhiyun kfree(master);
865*4882a593Smuzhiyun return rc;
866*4882a593Smuzhiyun }
867*4882a593Smuzhiyun
868*4882a593Smuzhiyun
869*4882a593Smuzhiyun
fsi_master_gpio_remove(struct platform_device * pdev)870*4882a593Smuzhiyun static int fsi_master_gpio_remove(struct platform_device *pdev)
871*4882a593Smuzhiyun {
872*4882a593Smuzhiyun struct fsi_master_gpio *master = platform_get_drvdata(pdev);
873*4882a593Smuzhiyun
874*4882a593Smuzhiyun device_remove_file(&pdev->dev, &dev_attr_external_mode);
875*4882a593Smuzhiyun
876*4882a593Smuzhiyun fsi_master_unregister(&master->master);
877*4882a593Smuzhiyun
878*4882a593Smuzhiyun return 0;
879*4882a593Smuzhiyun }
880*4882a593Smuzhiyun
881*4882a593Smuzhiyun static const struct of_device_id fsi_master_gpio_match[] = {
882*4882a593Smuzhiyun { .compatible = "fsi-master-gpio" },
883*4882a593Smuzhiyun { },
884*4882a593Smuzhiyun };
885*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, fsi_master_gpio_match);
886*4882a593Smuzhiyun
887*4882a593Smuzhiyun static struct platform_driver fsi_master_gpio_driver = {
888*4882a593Smuzhiyun .driver = {
889*4882a593Smuzhiyun .name = "fsi-master-gpio",
890*4882a593Smuzhiyun .of_match_table = fsi_master_gpio_match,
891*4882a593Smuzhiyun },
892*4882a593Smuzhiyun .probe = fsi_master_gpio_probe,
893*4882a593Smuzhiyun .remove = fsi_master_gpio_remove,
894*4882a593Smuzhiyun };
895*4882a593Smuzhiyun
896*4882a593Smuzhiyun module_platform_driver(fsi_master_gpio_driver);
897*4882a593Smuzhiyun MODULE_LICENSE("GPL");
898