1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun #ifndef __CF_FSI_FW_H 3*4882a593Smuzhiyun #define __CF_FSI_FW_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* 6*4882a593Smuzhiyun * uCode file layout 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * 0000...03ff : m68k exception vectors 9*4882a593Smuzhiyun * 0400...04ff : Header info & boot config block 10*4882a593Smuzhiyun * 0500....... : Code & stack 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* 14*4882a593Smuzhiyun * Header info & boot config area 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * The Header info is built into the ucode and provide version and 17*4882a593Smuzhiyun * platform information. 18*4882a593Smuzhiyun * 19*4882a593Smuzhiyun * the Boot config needs to be adjusted by the ARM prior to starting 20*4882a593Smuzhiyun * the ucode if the Command/Status area isn't at 0x320000 in CF space 21*4882a593Smuzhiyun * (ie. beginning of SRAM). 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define HDR_OFFSET 0x400 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* Info: Signature & version */ 27*4882a593Smuzhiyun #define HDR_SYS_SIG 0x00 /* 2 bytes system signature */ 28*4882a593Smuzhiyun #define SYS_SIG_SHARED 0x5348 29*4882a593Smuzhiyun #define SYS_SIG_SPLIT 0x5350 30*4882a593Smuzhiyun #define HDR_FW_VERS 0x02 /* 2 bytes Major.Minor */ 31*4882a593Smuzhiyun #define HDR_API_VERS 0x04 /* 2 bytes Major.Minor */ 32*4882a593Smuzhiyun #define API_VERSION_MAJ 2 /* Current version */ 33*4882a593Smuzhiyun #define API_VERSION_MIN 1 34*4882a593Smuzhiyun #define HDR_FW_OPTIONS 0x08 /* 4 bytes option flags */ 35*4882a593Smuzhiyun #define FW_OPTION_TRACE_EN 0x00000001 /* FW tracing enabled */ 36*4882a593Smuzhiyun #define FW_OPTION_CONT_CLOCK 0x00000002 /* Continuous clocking supported */ 37*4882a593Smuzhiyun #define HDR_FW_SIZE 0x10 /* 4 bytes size for combo image */ 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* Boot Config: Address of Command/Status area */ 40*4882a593Smuzhiyun #define HDR_CMD_STAT_AREA 0x80 /* 4 bytes CF address */ 41*4882a593Smuzhiyun #define HDR_FW_CONTROL 0x84 /* 4 bytes control flags */ 42*4882a593Smuzhiyun #define FW_CONTROL_CONT_CLOCK 0x00000002 /* Continuous clocking enabled */ 43*4882a593Smuzhiyun #define FW_CONTROL_DUMMY_RD 0x00000004 /* Extra dummy read (AST2400) */ 44*4882a593Smuzhiyun #define FW_CONTROL_USE_STOP 0x00000008 /* Use STOP instructions */ 45*4882a593Smuzhiyun #define HDR_CLOCK_GPIO_VADDR 0x90 /* 2 bytes offset from GPIO base */ 46*4882a593Smuzhiyun #define HDR_CLOCK_GPIO_DADDR 0x92 /* 2 bytes offset from GPIO base */ 47*4882a593Smuzhiyun #define HDR_DATA_GPIO_VADDR 0x94 /* 2 bytes offset from GPIO base */ 48*4882a593Smuzhiyun #define HDR_DATA_GPIO_DADDR 0x96 /* 2 bytes offset from GPIO base */ 49*4882a593Smuzhiyun #define HDR_TRANS_GPIO_VADDR 0x98 /* 2 bytes offset from GPIO base */ 50*4882a593Smuzhiyun #define HDR_TRANS_GPIO_DADDR 0x9a /* 2 bytes offset from GPIO base */ 51*4882a593Smuzhiyun #define HDR_CLOCK_GPIO_BIT 0x9c /* 1 byte bit number */ 52*4882a593Smuzhiyun #define HDR_DATA_GPIO_BIT 0x9d /* 1 byte bit number */ 53*4882a593Smuzhiyun #define HDR_TRANS_GPIO_BIT 0x9e /* 1 byte bit number */ 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* 56*4882a593Smuzhiyun * Command/Status area layout: Main part 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* Command/Status register: 60*4882a593Smuzhiyun * 61*4882a593Smuzhiyun * +---------------------------+ 62*4882a593Smuzhiyun * | STAT | RLEN | CLEN | CMD | 63*4882a593Smuzhiyun * | 8 | 8 | 8 | 8 | 64*4882a593Smuzhiyun * +---------------------------+ 65*4882a593Smuzhiyun * | | | | 66*4882a593Smuzhiyun * status | | | 67*4882a593Smuzhiyun * Response len | | 68*4882a593Smuzhiyun * (in bits) | | 69*4882a593Smuzhiyun * | | 70*4882a593Smuzhiyun * Command len | 71*4882a593Smuzhiyun * (in bits) | 72*4882a593Smuzhiyun * | 73*4882a593Smuzhiyun * Command code 74*4882a593Smuzhiyun * 75*4882a593Smuzhiyun * Due to the big endian layout, that means that a byte read will 76*4882a593Smuzhiyun * return the status byte 77*4882a593Smuzhiyun */ 78*4882a593Smuzhiyun #define CMD_STAT_REG 0x00 79*4882a593Smuzhiyun #define CMD_REG_CMD_MASK 0x000000ff 80*4882a593Smuzhiyun #define CMD_REG_CMD_SHIFT 0 81*4882a593Smuzhiyun #define CMD_NONE 0x00 82*4882a593Smuzhiyun #define CMD_COMMAND 0x01 83*4882a593Smuzhiyun #define CMD_BREAK 0x02 84*4882a593Smuzhiyun #define CMD_IDLE_CLOCKS 0x03 /* clen = #clocks */ 85*4882a593Smuzhiyun #define CMD_INVALID 0xff 86*4882a593Smuzhiyun #define CMD_REG_CLEN_MASK 0x0000ff00 87*4882a593Smuzhiyun #define CMD_REG_CLEN_SHIFT 8 88*4882a593Smuzhiyun #define CMD_REG_RLEN_MASK 0x00ff0000 89*4882a593Smuzhiyun #define CMD_REG_RLEN_SHIFT 16 90*4882a593Smuzhiyun #define CMD_REG_STAT_MASK 0xff000000 91*4882a593Smuzhiyun #define CMD_REG_STAT_SHIFT 24 92*4882a593Smuzhiyun #define STAT_WORKING 0x00 93*4882a593Smuzhiyun #define STAT_COMPLETE 0x01 94*4882a593Smuzhiyun #define STAT_ERR_INVAL_CMD 0x80 95*4882a593Smuzhiyun #define STAT_ERR_INVAL_IRQ 0x81 96*4882a593Smuzhiyun #define STAT_ERR_MTOE 0x82 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* Response tag & CRC */ 99*4882a593Smuzhiyun #define STAT_RTAG 0x04 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun /* Response CRC */ 102*4882a593Smuzhiyun #define STAT_RCRC 0x05 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* Echo and Send delay */ 105*4882a593Smuzhiyun #define ECHO_DLY_REG 0x08 106*4882a593Smuzhiyun #define SEND_DLY_REG 0x09 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /* Command data area 109*4882a593Smuzhiyun * 110*4882a593Smuzhiyun * Last byte of message must be left aligned 111*4882a593Smuzhiyun */ 112*4882a593Smuzhiyun #define CMD_DATA 0x10 /* 64 bit of data */ 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun /* Response data area, right aligned, unused top bits are 1 */ 115*4882a593Smuzhiyun #define RSP_DATA 0x20 /* 32 bit of data */ 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun /* Misc */ 118*4882a593Smuzhiyun #define INT_CNT 0x30 /* 32-bit interrupt count */ 119*4882a593Smuzhiyun #define BAD_INT_VEC 0x34 /* 32-bit bad interrupt vector # */ 120*4882a593Smuzhiyun #define CF_STARTED 0x38 /* byte, set to -1 when copro started */ 121*4882a593Smuzhiyun #define CLK_CNT 0x3c /* 32-bit, clock count (debug only) */ 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun /* 124*4882a593Smuzhiyun * SRAM layout: GPIO arbitration part 125*4882a593Smuzhiyun */ 126*4882a593Smuzhiyun #define ARB_REG 0x40 127*4882a593Smuzhiyun #define ARB_ARM_REQ 0x01 128*4882a593Smuzhiyun #define ARB_ARM_ACK 0x02 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun /* Misc2 */ 131*4882a593Smuzhiyun #define CF_RESET_D0 0x50 132*4882a593Smuzhiyun #define CF_RESET_D1 0x54 133*4882a593Smuzhiyun #define BAD_INT_S0 0x58 134*4882a593Smuzhiyun #define BAD_INT_S1 0x5c 135*4882a593Smuzhiyun #define STOP_CNT 0x60 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun /* Internal */ 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun /* 140*4882a593Smuzhiyun * SRAM layout: Trace buffer (debug builds only) 141*4882a593Smuzhiyun */ 142*4882a593Smuzhiyun #define TRACEBUF 0x100 143*4882a593Smuzhiyun #define TR_CLKOBIT0 0xc0 144*4882a593Smuzhiyun #define TR_CLKOBIT1 0xc1 145*4882a593Smuzhiyun #define TR_CLKOSTART 0x82 146*4882a593Smuzhiyun #define TR_OLEN 0x83 /* + len */ 147*4882a593Smuzhiyun #define TR_CLKZ 0x84 /* + count */ 148*4882a593Smuzhiyun #define TR_CLKWSTART 0x85 149*4882a593Smuzhiyun #define TR_CLKTAG 0x86 /* + tag */ 150*4882a593Smuzhiyun #define TR_CLKDATA 0x87 /* + len */ 151*4882a593Smuzhiyun #define TR_CLKCRC 0x88 /* + raw crc */ 152*4882a593Smuzhiyun #define TR_CLKIBIT0 0x90 153*4882a593Smuzhiyun #define TR_CLKIBIT1 0x91 154*4882a593Smuzhiyun #define TR_END 0xff 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun #endif /* __CF_FSI_FW_H */ 157*4882a593Smuzhiyun 158