1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * FPGA Manager Core
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2013-2015 Altera Corporation
6*4882a593Smuzhiyun * Copyright (C) 2017 Intel Corporation
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * With code from the mailing list:
9*4882a593Smuzhiyun * Copyright (C) 2013 Xilinx, Inc.
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun #include <linux/firmware.h>
12*4882a593Smuzhiyun #include <linux/fpga/fpga-mgr.h>
13*4882a593Smuzhiyun #include <linux/idr.h>
14*4882a593Smuzhiyun #include <linux/module.h>
15*4882a593Smuzhiyun #include <linux/of.h>
16*4882a593Smuzhiyun #include <linux/mutex.h>
17*4882a593Smuzhiyun #include <linux/slab.h>
18*4882a593Smuzhiyun #include <linux/scatterlist.h>
19*4882a593Smuzhiyun #include <linux/highmem.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun static DEFINE_IDA(fpga_mgr_ida);
22*4882a593Smuzhiyun static struct class *fpga_mgr_class;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /**
25*4882a593Smuzhiyun * fpga_image_info_alloc - Allocate a FPGA image info struct
26*4882a593Smuzhiyun * @dev: owning device
27*4882a593Smuzhiyun *
28*4882a593Smuzhiyun * Return: struct fpga_image_info or NULL
29*4882a593Smuzhiyun */
fpga_image_info_alloc(struct device * dev)30*4882a593Smuzhiyun struct fpga_image_info *fpga_image_info_alloc(struct device *dev)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun struct fpga_image_info *info;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun get_device(dev);
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
37*4882a593Smuzhiyun if (!info) {
38*4882a593Smuzhiyun put_device(dev);
39*4882a593Smuzhiyun return NULL;
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun info->dev = dev;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun return info;
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(fpga_image_info_alloc);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /**
49*4882a593Smuzhiyun * fpga_image_info_free - Free a FPGA image info struct
50*4882a593Smuzhiyun * @info: FPGA image info struct to free
51*4882a593Smuzhiyun */
fpga_image_info_free(struct fpga_image_info * info)52*4882a593Smuzhiyun void fpga_image_info_free(struct fpga_image_info *info)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun struct device *dev;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun if (!info)
57*4882a593Smuzhiyun return;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun dev = info->dev;
60*4882a593Smuzhiyun if (info->firmware_name)
61*4882a593Smuzhiyun devm_kfree(dev, info->firmware_name);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun devm_kfree(dev, info);
64*4882a593Smuzhiyun put_device(dev);
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(fpga_image_info_free);
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /*
69*4882a593Smuzhiyun * Call the low level driver's write_init function. This will do the
70*4882a593Smuzhiyun * device-specific things to get the FPGA into the state where it is ready to
71*4882a593Smuzhiyun * receive an FPGA image. The low level driver only gets to see the first
72*4882a593Smuzhiyun * initial_header_size bytes in the buffer.
73*4882a593Smuzhiyun */
fpga_mgr_write_init_buf(struct fpga_manager * mgr,struct fpga_image_info * info,const char * buf,size_t count)74*4882a593Smuzhiyun static int fpga_mgr_write_init_buf(struct fpga_manager *mgr,
75*4882a593Smuzhiyun struct fpga_image_info *info,
76*4882a593Smuzhiyun const char *buf, size_t count)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun int ret;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun mgr->state = FPGA_MGR_STATE_WRITE_INIT;
81*4882a593Smuzhiyun if (!mgr->mops->initial_header_size)
82*4882a593Smuzhiyun ret = mgr->mops->write_init(mgr, info, NULL, 0);
83*4882a593Smuzhiyun else
84*4882a593Smuzhiyun ret = mgr->mops->write_init(
85*4882a593Smuzhiyun mgr, info, buf, min(mgr->mops->initial_header_size, count));
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun if (ret) {
88*4882a593Smuzhiyun dev_err(&mgr->dev, "Error preparing FPGA for writing\n");
89*4882a593Smuzhiyun mgr->state = FPGA_MGR_STATE_WRITE_INIT_ERR;
90*4882a593Smuzhiyun return ret;
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun return 0;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
fpga_mgr_write_init_sg(struct fpga_manager * mgr,struct fpga_image_info * info,struct sg_table * sgt)96*4882a593Smuzhiyun static int fpga_mgr_write_init_sg(struct fpga_manager *mgr,
97*4882a593Smuzhiyun struct fpga_image_info *info,
98*4882a593Smuzhiyun struct sg_table *sgt)
99*4882a593Smuzhiyun {
100*4882a593Smuzhiyun struct sg_mapping_iter miter;
101*4882a593Smuzhiyun size_t len;
102*4882a593Smuzhiyun char *buf;
103*4882a593Smuzhiyun int ret;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun if (!mgr->mops->initial_header_size)
106*4882a593Smuzhiyun return fpga_mgr_write_init_buf(mgr, info, NULL, 0);
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun /*
109*4882a593Smuzhiyun * First try to use miter to map the first fragment to access the
110*4882a593Smuzhiyun * header, this is the typical path.
111*4882a593Smuzhiyun */
112*4882a593Smuzhiyun sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG);
113*4882a593Smuzhiyun if (sg_miter_next(&miter) &&
114*4882a593Smuzhiyun miter.length >= mgr->mops->initial_header_size) {
115*4882a593Smuzhiyun ret = fpga_mgr_write_init_buf(mgr, info, miter.addr,
116*4882a593Smuzhiyun miter.length);
117*4882a593Smuzhiyun sg_miter_stop(&miter);
118*4882a593Smuzhiyun return ret;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun sg_miter_stop(&miter);
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun /* Otherwise copy the fragments into temporary memory. */
123*4882a593Smuzhiyun buf = kmalloc(mgr->mops->initial_header_size, GFP_KERNEL);
124*4882a593Smuzhiyun if (!buf)
125*4882a593Smuzhiyun return -ENOMEM;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun len = sg_copy_to_buffer(sgt->sgl, sgt->nents, buf,
128*4882a593Smuzhiyun mgr->mops->initial_header_size);
129*4882a593Smuzhiyun ret = fpga_mgr_write_init_buf(mgr, info, buf, len);
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun kfree(buf);
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun return ret;
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun /*
137*4882a593Smuzhiyun * After all the FPGA image has been written, do the device specific steps to
138*4882a593Smuzhiyun * finish and set the FPGA into operating mode.
139*4882a593Smuzhiyun */
fpga_mgr_write_complete(struct fpga_manager * mgr,struct fpga_image_info * info)140*4882a593Smuzhiyun static int fpga_mgr_write_complete(struct fpga_manager *mgr,
141*4882a593Smuzhiyun struct fpga_image_info *info)
142*4882a593Smuzhiyun {
143*4882a593Smuzhiyun int ret;
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun mgr->state = FPGA_MGR_STATE_WRITE_COMPLETE;
146*4882a593Smuzhiyun ret = mgr->mops->write_complete(mgr, info);
147*4882a593Smuzhiyun if (ret) {
148*4882a593Smuzhiyun dev_err(&mgr->dev, "Error after writing image data to FPGA\n");
149*4882a593Smuzhiyun mgr->state = FPGA_MGR_STATE_WRITE_COMPLETE_ERR;
150*4882a593Smuzhiyun return ret;
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun mgr->state = FPGA_MGR_STATE_OPERATING;
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun return 0;
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun /**
158*4882a593Smuzhiyun * fpga_mgr_buf_load_sg - load fpga from image in buffer from a scatter list
159*4882a593Smuzhiyun * @mgr: fpga manager
160*4882a593Smuzhiyun * @info: fpga image specific information
161*4882a593Smuzhiyun * @sgt: scatterlist table
162*4882a593Smuzhiyun *
163*4882a593Smuzhiyun * Step the low level fpga manager through the device-specific steps of getting
164*4882a593Smuzhiyun * an FPGA ready to be configured, writing the image to it, then doing whatever
165*4882a593Smuzhiyun * post-configuration steps necessary. This code assumes the caller got the
166*4882a593Smuzhiyun * mgr pointer from of_fpga_mgr_get() or fpga_mgr_get() and checked that it is
167*4882a593Smuzhiyun * not an error code.
168*4882a593Smuzhiyun *
169*4882a593Smuzhiyun * This is the preferred entry point for FPGA programming, it does not require
170*4882a593Smuzhiyun * any contiguous kernel memory.
171*4882a593Smuzhiyun *
172*4882a593Smuzhiyun * Return: 0 on success, negative error code otherwise.
173*4882a593Smuzhiyun */
fpga_mgr_buf_load_sg(struct fpga_manager * mgr,struct fpga_image_info * info,struct sg_table * sgt)174*4882a593Smuzhiyun static int fpga_mgr_buf_load_sg(struct fpga_manager *mgr,
175*4882a593Smuzhiyun struct fpga_image_info *info,
176*4882a593Smuzhiyun struct sg_table *sgt)
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun int ret;
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun ret = fpga_mgr_write_init_sg(mgr, info, sgt);
181*4882a593Smuzhiyun if (ret)
182*4882a593Smuzhiyun return ret;
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun /* Write the FPGA image to the FPGA. */
185*4882a593Smuzhiyun mgr->state = FPGA_MGR_STATE_WRITE;
186*4882a593Smuzhiyun if (mgr->mops->write_sg) {
187*4882a593Smuzhiyun ret = mgr->mops->write_sg(mgr, sgt);
188*4882a593Smuzhiyun } else {
189*4882a593Smuzhiyun struct sg_mapping_iter miter;
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG);
192*4882a593Smuzhiyun while (sg_miter_next(&miter)) {
193*4882a593Smuzhiyun ret = mgr->mops->write(mgr, miter.addr, miter.length);
194*4882a593Smuzhiyun if (ret)
195*4882a593Smuzhiyun break;
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun sg_miter_stop(&miter);
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun if (ret) {
201*4882a593Smuzhiyun dev_err(&mgr->dev, "Error while writing image data to FPGA\n");
202*4882a593Smuzhiyun mgr->state = FPGA_MGR_STATE_WRITE_ERR;
203*4882a593Smuzhiyun return ret;
204*4882a593Smuzhiyun }
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun return fpga_mgr_write_complete(mgr, info);
207*4882a593Smuzhiyun }
208*4882a593Smuzhiyun
fpga_mgr_buf_load_mapped(struct fpga_manager * mgr,struct fpga_image_info * info,const char * buf,size_t count)209*4882a593Smuzhiyun static int fpga_mgr_buf_load_mapped(struct fpga_manager *mgr,
210*4882a593Smuzhiyun struct fpga_image_info *info,
211*4882a593Smuzhiyun const char *buf, size_t count)
212*4882a593Smuzhiyun {
213*4882a593Smuzhiyun int ret;
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun ret = fpga_mgr_write_init_buf(mgr, info, buf, count);
216*4882a593Smuzhiyun if (ret)
217*4882a593Smuzhiyun return ret;
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun /*
220*4882a593Smuzhiyun * Write the FPGA image to the FPGA.
221*4882a593Smuzhiyun */
222*4882a593Smuzhiyun mgr->state = FPGA_MGR_STATE_WRITE;
223*4882a593Smuzhiyun ret = mgr->mops->write(mgr, buf, count);
224*4882a593Smuzhiyun if (ret) {
225*4882a593Smuzhiyun dev_err(&mgr->dev, "Error while writing image data to FPGA\n");
226*4882a593Smuzhiyun mgr->state = FPGA_MGR_STATE_WRITE_ERR;
227*4882a593Smuzhiyun return ret;
228*4882a593Smuzhiyun }
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun return fpga_mgr_write_complete(mgr, info);
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun /**
234*4882a593Smuzhiyun * fpga_mgr_buf_load - load fpga from image in buffer
235*4882a593Smuzhiyun * @mgr: fpga manager
236*4882a593Smuzhiyun * @info: fpga image info
237*4882a593Smuzhiyun * @buf: buffer contain fpga image
238*4882a593Smuzhiyun * @count: byte count of buf
239*4882a593Smuzhiyun *
240*4882a593Smuzhiyun * Step the low level fpga manager through the device-specific steps of getting
241*4882a593Smuzhiyun * an FPGA ready to be configured, writing the image to it, then doing whatever
242*4882a593Smuzhiyun * post-configuration steps necessary. This code assumes the caller got the
243*4882a593Smuzhiyun * mgr pointer from of_fpga_mgr_get() and checked that it is not an error code.
244*4882a593Smuzhiyun *
245*4882a593Smuzhiyun * Return: 0 on success, negative error code otherwise.
246*4882a593Smuzhiyun */
fpga_mgr_buf_load(struct fpga_manager * mgr,struct fpga_image_info * info,const char * buf,size_t count)247*4882a593Smuzhiyun static int fpga_mgr_buf_load(struct fpga_manager *mgr,
248*4882a593Smuzhiyun struct fpga_image_info *info,
249*4882a593Smuzhiyun const char *buf, size_t count)
250*4882a593Smuzhiyun {
251*4882a593Smuzhiyun struct page **pages;
252*4882a593Smuzhiyun struct sg_table sgt;
253*4882a593Smuzhiyun const void *p;
254*4882a593Smuzhiyun int nr_pages;
255*4882a593Smuzhiyun int index;
256*4882a593Smuzhiyun int rc;
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun /*
259*4882a593Smuzhiyun * This is just a fast path if the caller has already created a
260*4882a593Smuzhiyun * contiguous kernel buffer and the driver doesn't require SG, non-SG
261*4882a593Smuzhiyun * drivers will still work on the slow path.
262*4882a593Smuzhiyun */
263*4882a593Smuzhiyun if (mgr->mops->write)
264*4882a593Smuzhiyun return fpga_mgr_buf_load_mapped(mgr, info, buf, count);
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun /*
267*4882a593Smuzhiyun * Convert the linear kernel pointer into a sg_table of pages for use
268*4882a593Smuzhiyun * by the driver.
269*4882a593Smuzhiyun */
270*4882a593Smuzhiyun nr_pages = DIV_ROUND_UP((unsigned long)buf + count, PAGE_SIZE) -
271*4882a593Smuzhiyun (unsigned long)buf / PAGE_SIZE;
272*4882a593Smuzhiyun pages = kmalloc_array(nr_pages, sizeof(struct page *), GFP_KERNEL);
273*4882a593Smuzhiyun if (!pages)
274*4882a593Smuzhiyun return -ENOMEM;
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun p = buf - offset_in_page(buf);
277*4882a593Smuzhiyun for (index = 0; index < nr_pages; index++) {
278*4882a593Smuzhiyun if (is_vmalloc_addr(p))
279*4882a593Smuzhiyun pages[index] = vmalloc_to_page(p);
280*4882a593Smuzhiyun else
281*4882a593Smuzhiyun pages[index] = kmap_to_page((void *)p);
282*4882a593Smuzhiyun if (!pages[index]) {
283*4882a593Smuzhiyun kfree(pages);
284*4882a593Smuzhiyun return -EFAULT;
285*4882a593Smuzhiyun }
286*4882a593Smuzhiyun p += PAGE_SIZE;
287*4882a593Smuzhiyun }
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun /*
290*4882a593Smuzhiyun * The temporary pages list is used to code share the merging algorithm
291*4882a593Smuzhiyun * in sg_alloc_table_from_pages
292*4882a593Smuzhiyun */
293*4882a593Smuzhiyun rc = sg_alloc_table_from_pages(&sgt, pages, index, offset_in_page(buf),
294*4882a593Smuzhiyun count, GFP_KERNEL);
295*4882a593Smuzhiyun kfree(pages);
296*4882a593Smuzhiyun if (rc)
297*4882a593Smuzhiyun return rc;
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun rc = fpga_mgr_buf_load_sg(mgr, info, &sgt);
300*4882a593Smuzhiyun sg_free_table(&sgt);
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun return rc;
303*4882a593Smuzhiyun }
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun /**
306*4882a593Smuzhiyun * fpga_mgr_firmware_load - request firmware and load to fpga
307*4882a593Smuzhiyun * @mgr: fpga manager
308*4882a593Smuzhiyun * @info: fpga image specific information
309*4882a593Smuzhiyun * @image_name: name of image file on the firmware search path
310*4882a593Smuzhiyun *
311*4882a593Smuzhiyun * Request an FPGA image using the firmware class, then write out to the FPGA.
312*4882a593Smuzhiyun * Update the state before each step to provide info on what step failed if
313*4882a593Smuzhiyun * there is a failure. This code assumes the caller got the mgr pointer
314*4882a593Smuzhiyun * from of_fpga_mgr_get() or fpga_mgr_get() and checked that it is not an error
315*4882a593Smuzhiyun * code.
316*4882a593Smuzhiyun *
317*4882a593Smuzhiyun * Return: 0 on success, negative error code otherwise.
318*4882a593Smuzhiyun */
fpga_mgr_firmware_load(struct fpga_manager * mgr,struct fpga_image_info * info,const char * image_name)319*4882a593Smuzhiyun static int fpga_mgr_firmware_load(struct fpga_manager *mgr,
320*4882a593Smuzhiyun struct fpga_image_info *info,
321*4882a593Smuzhiyun const char *image_name)
322*4882a593Smuzhiyun {
323*4882a593Smuzhiyun struct device *dev = &mgr->dev;
324*4882a593Smuzhiyun const struct firmware *fw;
325*4882a593Smuzhiyun int ret;
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun dev_info(dev, "writing %s to %s\n", image_name, mgr->name);
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun mgr->state = FPGA_MGR_STATE_FIRMWARE_REQ;
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun ret = request_firmware(&fw, image_name, dev);
332*4882a593Smuzhiyun if (ret) {
333*4882a593Smuzhiyun mgr->state = FPGA_MGR_STATE_FIRMWARE_REQ_ERR;
334*4882a593Smuzhiyun dev_err(dev, "Error requesting firmware %s\n", image_name);
335*4882a593Smuzhiyun return ret;
336*4882a593Smuzhiyun }
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun ret = fpga_mgr_buf_load(mgr, info, fw->data, fw->size);
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun release_firmware(fw);
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun return ret;
343*4882a593Smuzhiyun }
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun /**
346*4882a593Smuzhiyun * fpga_mgr_load - load FPGA from scatter/gather table, buffer, or firmware
347*4882a593Smuzhiyun * @mgr: fpga manager
348*4882a593Smuzhiyun * @info: fpga image information.
349*4882a593Smuzhiyun *
350*4882a593Smuzhiyun * Load the FPGA from an image which is indicated in @info. If successful, the
351*4882a593Smuzhiyun * FPGA ends up in operating mode.
352*4882a593Smuzhiyun *
353*4882a593Smuzhiyun * Return: 0 on success, negative error code otherwise.
354*4882a593Smuzhiyun */
fpga_mgr_load(struct fpga_manager * mgr,struct fpga_image_info * info)355*4882a593Smuzhiyun int fpga_mgr_load(struct fpga_manager *mgr, struct fpga_image_info *info)
356*4882a593Smuzhiyun {
357*4882a593Smuzhiyun if (info->sgt)
358*4882a593Smuzhiyun return fpga_mgr_buf_load_sg(mgr, info, info->sgt);
359*4882a593Smuzhiyun if (info->buf && info->count)
360*4882a593Smuzhiyun return fpga_mgr_buf_load(mgr, info, info->buf, info->count);
361*4882a593Smuzhiyun if (info->firmware_name)
362*4882a593Smuzhiyun return fpga_mgr_firmware_load(mgr, info, info->firmware_name);
363*4882a593Smuzhiyun return -EINVAL;
364*4882a593Smuzhiyun }
365*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(fpga_mgr_load);
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun static const char * const state_str[] = {
368*4882a593Smuzhiyun [FPGA_MGR_STATE_UNKNOWN] = "unknown",
369*4882a593Smuzhiyun [FPGA_MGR_STATE_POWER_OFF] = "power off",
370*4882a593Smuzhiyun [FPGA_MGR_STATE_POWER_UP] = "power up",
371*4882a593Smuzhiyun [FPGA_MGR_STATE_RESET] = "reset",
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun /* requesting FPGA image from firmware */
374*4882a593Smuzhiyun [FPGA_MGR_STATE_FIRMWARE_REQ] = "firmware request",
375*4882a593Smuzhiyun [FPGA_MGR_STATE_FIRMWARE_REQ_ERR] = "firmware request error",
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun /* Preparing FPGA to receive image */
378*4882a593Smuzhiyun [FPGA_MGR_STATE_WRITE_INIT] = "write init",
379*4882a593Smuzhiyun [FPGA_MGR_STATE_WRITE_INIT_ERR] = "write init error",
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun /* Writing image to FPGA */
382*4882a593Smuzhiyun [FPGA_MGR_STATE_WRITE] = "write",
383*4882a593Smuzhiyun [FPGA_MGR_STATE_WRITE_ERR] = "write error",
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun /* Finishing configuration after image has been written */
386*4882a593Smuzhiyun [FPGA_MGR_STATE_WRITE_COMPLETE] = "write complete",
387*4882a593Smuzhiyun [FPGA_MGR_STATE_WRITE_COMPLETE_ERR] = "write complete error",
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun /* FPGA reports to be in normal operating mode */
390*4882a593Smuzhiyun [FPGA_MGR_STATE_OPERATING] = "operating",
391*4882a593Smuzhiyun };
392*4882a593Smuzhiyun
name_show(struct device * dev,struct device_attribute * attr,char * buf)393*4882a593Smuzhiyun static ssize_t name_show(struct device *dev,
394*4882a593Smuzhiyun struct device_attribute *attr, char *buf)
395*4882a593Smuzhiyun {
396*4882a593Smuzhiyun struct fpga_manager *mgr = to_fpga_manager(dev);
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun return sprintf(buf, "%s\n", mgr->name);
399*4882a593Smuzhiyun }
400*4882a593Smuzhiyun
state_show(struct device * dev,struct device_attribute * attr,char * buf)401*4882a593Smuzhiyun static ssize_t state_show(struct device *dev,
402*4882a593Smuzhiyun struct device_attribute *attr, char *buf)
403*4882a593Smuzhiyun {
404*4882a593Smuzhiyun struct fpga_manager *mgr = to_fpga_manager(dev);
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun return sprintf(buf, "%s\n", state_str[mgr->state]);
407*4882a593Smuzhiyun }
408*4882a593Smuzhiyun
status_show(struct device * dev,struct device_attribute * attr,char * buf)409*4882a593Smuzhiyun static ssize_t status_show(struct device *dev,
410*4882a593Smuzhiyun struct device_attribute *attr, char *buf)
411*4882a593Smuzhiyun {
412*4882a593Smuzhiyun struct fpga_manager *mgr = to_fpga_manager(dev);
413*4882a593Smuzhiyun u64 status;
414*4882a593Smuzhiyun int len = 0;
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun if (!mgr->mops->status)
417*4882a593Smuzhiyun return -ENOENT;
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun status = mgr->mops->status(mgr);
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun if (status & FPGA_MGR_STATUS_OPERATION_ERR)
422*4882a593Smuzhiyun len += sprintf(buf + len, "reconfig operation error\n");
423*4882a593Smuzhiyun if (status & FPGA_MGR_STATUS_CRC_ERR)
424*4882a593Smuzhiyun len += sprintf(buf + len, "reconfig CRC error\n");
425*4882a593Smuzhiyun if (status & FPGA_MGR_STATUS_INCOMPATIBLE_IMAGE_ERR)
426*4882a593Smuzhiyun len += sprintf(buf + len, "reconfig incompatible image\n");
427*4882a593Smuzhiyun if (status & FPGA_MGR_STATUS_IP_PROTOCOL_ERR)
428*4882a593Smuzhiyun len += sprintf(buf + len, "reconfig IP protocol error\n");
429*4882a593Smuzhiyun if (status & FPGA_MGR_STATUS_FIFO_OVERFLOW_ERR)
430*4882a593Smuzhiyun len += sprintf(buf + len, "reconfig fifo overflow error\n");
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun return len;
433*4882a593Smuzhiyun }
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun static DEVICE_ATTR_RO(name);
436*4882a593Smuzhiyun static DEVICE_ATTR_RO(state);
437*4882a593Smuzhiyun static DEVICE_ATTR_RO(status);
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun static struct attribute *fpga_mgr_attrs[] = {
440*4882a593Smuzhiyun &dev_attr_name.attr,
441*4882a593Smuzhiyun &dev_attr_state.attr,
442*4882a593Smuzhiyun &dev_attr_status.attr,
443*4882a593Smuzhiyun NULL,
444*4882a593Smuzhiyun };
445*4882a593Smuzhiyun ATTRIBUTE_GROUPS(fpga_mgr);
446*4882a593Smuzhiyun
__fpga_mgr_get(struct device * dev)447*4882a593Smuzhiyun static struct fpga_manager *__fpga_mgr_get(struct device *dev)
448*4882a593Smuzhiyun {
449*4882a593Smuzhiyun struct fpga_manager *mgr;
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun mgr = to_fpga_manager(dev);
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun if (!try_module_get(dev->parent->driver->owner))
454*4882a593Smuzhiyun goto err_dev;
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun return mgr;
457*4882a593Smuzhiyun
458*4882a593Smuzhiyun err_dev:
459*4882a593Smuzhiyun put_device(dev);
460*4882a593Smuzhiyun return ERR_PTR(-ENODEV);
461*4882a593Smuzhiyun }
462*4882a593Smuzhiyun
fpga_mgr_dev_match(struct device * dev,const void * data)463*4882a593Smuzhiyun static int fpga_mgr_dev_match(struct device *dev, const void *data)
464*4882a593Smuzhiyun {
465*4882a593Smuzhiyun return dev->parent == data;
466*4882a593Smuzhiyun }
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun /**
469*4882a593Smuzhiyun * fpga_mgr_get - Given a device, get a reference to a fpga mgr.
470*4882a593Smuzhiyun * @dev: parent device that fpga mgr was registered with
471*4882a593Smuzhiyun *
472*4882a593Smuzhiyun * Return: fpga manager struct or IS_ERR() condition containing error code.
473*4882a593Smuzhiyun */
fpga_mgr_get(struct device * dev)474*4882a593Smuzhiyun struct fpga_manager *fpga_mgr_get(struct device *dev)
475*4882a593Smuzhiyun {
476*4882a593Smuzhiyun struct device *mgr_dev = class_find_device(fpga_mgr_class, NULL, dev,
477*4882a593Smuzhiyun fpga_mgr_dev_match);
478*4882a593Smuzhiyun if (!mgr_dev)
479*4882a593Smuzhiyun return ERR_PTR(-ENODEV);
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun return __fpga_mgr_get(mgr_dev);
482*4882a593Smuzhiyun }
483*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(fpga_mgr_get);
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun /**
486*4882a593Smuzhiyun * of_fpga_mgr_get - Given a device node, get a reference to a fpga mgr.
487*4882a593Smuzhiyun *
488*4882a593Smuzhiyun * @node: device node
489*4882a593Smuzhiyun *
490*4882a593Smuzhiyun * Return: fpga manager struct or IS_ERR() condition containing error code.
491*4882a593Smuzhiyun */
of_fpga_mgr_get(struct device_node * node)492*4882a593Smuzhiyun struct fpga_manager *of_fpga_mgr_get(struct device_node *node)
493*4882a593Smuzhiyun {
494*4882a593Smuzhiyun struct device *dev;
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun dev = class_find_device_by_of_node(fpga_mgr_class, node);
497*4882a593Smuzhiyun if (!dev)
498*4882a593Smuzhiyun return ERR_PTR(-ENODEV);
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun return __fpga_mgr_get(dev);
501*4882a593Smuzhiyun }
502*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(of_fpga_mgr_get);
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun /**
505*4882a593Smuzhiyun * fpga_mgr_put - release a reference to a fpga manager
506*4882a593Smuzhiyun * @mgr: fpga manager structure
507*4882a593Smuzhiyun */
fpga_mgr_put(struct fpga_manager * mgr)508*4882a593Smuzhiyun void fpga_mgr_put(struct fpga_manager *mgr)
509*4882a593Smuzhiyun {
510*4882a593Smuzhiyun module_put(mgr->dev.parent->driver->owner);
511*4882a593Smuzhiyun put_device(&mgr->dev);
512*4882a593Smuzhiyun }
513*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(fpga_mgr_put);
514*4882a593Smuzhiyun
515*4882a593Smuzhiyun /**
516*4882a593Smuzhiyun * fpga_mgr_lock - Lock FPGA manager for exclusive use
517*4882a593Smuzhiyun * @mgr: fpga manager
518*4882a593Smuzhiyun *
519*4882a593Smuzhiyun * Given a pointer to FPGA Manager (from fpga_mgr_get() or
520*4882a593Smuzhiyun * of_fpga_mgr_put()) attempt to get the mutex. The user should call
521*4882a593Smuzhiyun * fpga_mgr_lock() and verify that it returns 0 before attempting to
522*4882a593Smuzhiyun * program the FPGA. Likewise, the user should call fpga_mgr_unlock
523*4882a593Smuzhiyun * when done programming the FPGA.
524*4882a593Smuzhiyun *
525*4882a593Smuzhiyun * Return: 0 for success or -EBUSY
526*4882a593Smuzhiyun */
fpga_mgr_lock(struct fpga_manager * mgr)527*4882a593Smuzhiyun int fpga_mgr_lock(struct fpga_manager *mgr)
528*4882a593Smuzhiyun {
529*4882a593Smuzhiyun if (!mutex_trylock(&mgr->ref_mutex)) {
530*4882a593Smuzhiyun dev_err(&mgr->dev, "FPGA manager is in use.\n");
531*4882a593Smuzhiyun return -EBUSY;
532*4882a593Smuzhiyun }
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun return 0;
535*4882a593Smuzhiyun }
536*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(fpga_mgr_lock);
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun /**
539*4882a593Smuzhiyun * fpga_mgr_unlock - Unlock FPGA manager after done programming
540*4882a593Smuzhiyun * @mgr: fpga manager
541*4882a593Smuzhiyun */
fpga_mgr_unlock(struct fpga_manager * mgr)542*4882a593Smuzhiyun void fpga_mgr_unlock(struct fpga_manager *mgr)
543*4882a593Smuzhiyun {
544*4882a593Smuzhiyun mutex_unlock(&mgr->ref_mutex);
545*4882a593Smuzhiyun }
546*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(fpga_mgr_unlock);
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun /**
549*4882a593Smuzhiyun * fpga_mgr_create - create and initialize a FPGA manager struct
550*4882a593Smuzhiyun * @dev: fpga manager device from pdev
551*4882a593Smuzhiyun * @name: fpga manager name
552*4882a593Smuzhiyun * @mops: pointer to structure of fpga manager ops
553*4882a593Smuzhiyun * @priv: fpga manager private data
554*4882a593Smuzhiyun *
555*4882a593Smuzhiyun * The caller of this function is responsible for freeing the struct with
556*4882a593Smuzhiyun * fpga_mgr_free(). Using devm_fpga_mgr_create() instead is recommended.
557*4882a593Smuzhiyun *
558*4882a593Smuzhiyun * Return: pointer to struct fpga_manager or NULL
559*4882a593Smuzhiyun */
fpga_mgr_create(struct device * dev,const char * name,const struct fpga_manager_ops * mops,void * priv)560*4882a593Smuzhiyun struct fpga_manager *fpga_mgr_create(struct device *dev, const char *name,
561*4882a593Smuzhiyun const struct fpga_manager_ops *mops,
562*4882a593Smuzhiyun void *priv)
563*4882a593Smuzhiyun {
564*4882a593Smuzhiyun struct fpga_manager *mgr;
565*4882a593Smuzhiyun int id, ret;
566*4882a593Smuzhiyun
567*4882a593Smuzhiyun if (!mops || !mops->write_complete || !mops->state ||
568*4882a593Smuzhiyun !mops->write_init || (!mops->write && !mops->write_sg) ||
569*4882a593Smuzhiyun (mops->write && mops->write_sg)) {
570*4882a593Smuzhiyun dev_err(dev, "Attempt to register without fpga_manager_ops\n");
571*4882a593Smuzhiyun return NULL;
572*4882a593Smuzhiyun }
573*4882a593Smuzhiyun
574*4882a593Smuzhiyun if (!name || !strlen(name)) {
575*4882a593Smuzhiyun dev_err(dev, "Attempt to register with no name!\n");
576*4882a593Smuzhiyun return NULL;
577*4882a593Smuzhiyun }
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
580*4882a593Smuzhiyun if (!mgr)
581*4882a593Smuzhiyun return NULL;
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun id = ida_simple_get(&fpga_mgr_ida, 0, 0, GFP_KERNEL);
584*4882a593Smuzhiyun if (id < 0)
585*4882a593Smuzhiyun goto error_kfree;
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun mutex_init(&mgr->ref_mutex);
588*4882a593Smuzhiyun
589*4882a593Smuzhiyun mgr->name = name;
590*4882a593Smuzhiyun mgr->mops = mops;
591*4882a593Smuzhiyun mgr->priv = priv;
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun device_initialize(&mgr->dev);
594*4882a593Smuzhiyun mgr->dev.class = fpga_mgr_class;
595*4882a593Smuzhiyun mgr->dev.groups = mops->groups;
596*4882a593Smuzhiyun mgr->dev.parent = dev;
597*4882a593Smuzhiyun mgr->dev.of_node = dev->of_node;
598*4882a593Smuzhiyun mgr->dev.id = id;
599*4882a593Smuzhiyun
600*4882a593Smuzhiyun ret = dev_set_name(&mgr->dev, "fpga%d", id);
601*4882a593Smuzhiyun if (ret)
602*4882a593Smuzhiyun goto error_device;
603*4882a593Smuzhiyun
604*4882a593Smuzhiyun return mgr;
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun error_device:
607*4882a593Smuzhiyun ida_simple_remove(&fpga_mgr_ida, id);
608*4882a593Smuzhiyun error_kfree:
609*4882a593Smuzhiyun kfree(mgr);
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun return NULL;
612*4882a593Smuzhiyun }
613*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(fpga_mgr_create);
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun /**
616*4882a593Smuzhiyun * fpga_mgr_free - free a FPGA manager created with fpga_mgr_create()
617*4882a593Smuzhiyun * @mgr: fpga manager struct
618*4882a593Smuzhiyun */
fpga_mgr_free(struct fpga_manager * mgr)619*4882a593Smuzhiyun void fpga_mgr_free(struct fpga_manager *mgr)
620*4882a593Smuzhiyun {
621*4882a593Smuzhiyun ida_simple_remove(&fpga_mgr_ida, mgr->dev.id);
622*4882a593Smuzhiyun kfree(mgr);
623*4882a593Smuzhiyun }
624*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(fpga_mgr_free);
625*4882a593Smuzhiyun
devm_fpga_mgr_release(struct device * dev,void * res)626*4882a593Smuzhiyun static void devm_fpga_mgr_release(struct device *dev, void *res)
627*4882a593Smuzhiyun {
628*4882a593Smuzhiyun struct fpga_manager *mgr = *(struct fpga_manager **)res;
629*4882a593Smuzhiyun
630*4882a593Smuzhiyun fpga_mgr_free(mgr);
631*4882a593Smuzhiyun }
632*4882a593Smuzhiyun
633*4882a593Smuzhiyun /**
634*4882a593Smuzhiyun * devm_fpga_mgr_create - create and initialize a managed FPGA manager struct
635*4882a593Smuzhiyun * @dev: fpga manager device from pdev
636*4882a593Smuzhiyun * @name: fpga manager name
637*4882a593Smuzhiyun * @mops: pointer to structure of fpga manager ops
638*4882a593Smuzhiyun * @priv: fpga manager private data
639*4882a593Smuzhiyun *
640*4882a593Smuzhiyun * This function is intended for use in a FPGA manager driver's probe function.
641*4882a593Smuzhiyun * After the manager driver creates the manager struct with
642*4882a593Smuzhiyun * devm_fpga_mgr_create(), it should register it with fpga_mgr_register(). The
643*4882a593Smuzhiyun * manager driver's remove function should call fpga_mgr_unregister(). The
644*4882a593Smuzhiyun * manager struct allocated with this function will be freed automatically on
645*4882a593Smuzhiyun * driver detach. This includes the case of a probe function returning error
646*4882a593Smuzhiyun * before calling fpga_mgr_register(), the struct will still get cleaned up.
647*4882a593Smuzhiyun *
648*4882a593Smuzhiyun * Return: pointer to struct fpga_manager or NULL
649*4882a593Smuzhiyun */
devm_fpga_mgr_create(struct device * dev,const char * name,const struct fpga_manager_ops * mops,void * priv)650*4882a593Smuzhiyun struct fpga_manager *devm_fpga_mgr_create(struct device *dev, const char *name,
651*4882a593Smuzhiyun const struct fpga_manager_ops *mops,
652*4882a593Smuzhiyun void *priv)
653*4882a593Smuzhiyun {
654*4882a593Smuzhiyun struct fpga_manager **ptr, *mgr;
655*4882a593Smuzhiyun
656*4882a593Smuzhiyun ptr = devres_alloc(devm_fpga_mgr_release, sizeof(*ptr), GFP_KERNEL);
657*4882a593Smuzhiyun if (!ptr)
658*4882a593Smuzhiyun return NULL;
659*4882a593Smuzhiyun
660*4882a593Smuzhiyun mgr = fpga_mgr_create(dev, name, mops, priv);
661*4882a593Smuzhiyun if (!mgr) {
662*4882a593Smuzhiyun devres_free(ptr);
663*4882a593Smuzhiyun } else {
664*4882a593Smuzhiyun *ptr = mgr;
665*4882a593Smuzhiyun devres_add(dev, ptr);
666*4882a593Smuzhiyun }
667*4882a593Smuzhiyun
668*4882a593Smuzhiyun return mgr;
669*4882a593Smuzhiyun }
670*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(devm_fpga_mgr_create);
671*4882a593Smuzhiyun
672*4882a593Smuzhiyun /**
673*4882a593Smuzhiyun * fpga_mgr_register - register a FPGA manager
674*4882a593Smuzhiyun * @mgr: fpga manager struct
675*4882a593Smuzhiyun *
676*4882a593Smuzhiyun * Return: 0 on success, negative error code otherwise.
677*4882a593Smuzhiyun */
fpga_mgr_register(struct fpga_manager * mgr)678*4882a593Smuzhiyun int fpga_mgr_register(struct fpga_manager *mgr)
679*4882a593Smuzhiyun {
680*4882a593Smuzhiyun int ret;
681*4882a593Smuzhiyun
682*4882a593Smuzhiyun /*
683*4882a593Smuzhiyun * Initialize framework state by requesting low level driver read state
684*4882a593Smuzhiyun * from device. FPGA may be in reset mode or may have been programmed
685*4882a593Smuzhiyun * by bootloader or EEPROM.
686*4882a593Smuzhiyun */
687*4882a593Smuzhiyun mgr->state = mgr->mops->state(mgr);
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun ret = device_add(&mgr->dev);
690*4882a593Smuzhiyun if (ret)
691*4882a593Smuzhiyun goto error_device;
692*4882a593Smuzhiyun
693*4882a593Smuzhiyun dev_info(&mgr->dev, "%s registered\n", mgr->name);
694*4882a593Smuzhiyun
695*4882a593Smuzhiyun return 0;
696*4882a593Smuzhiyun
697*4882a593Smuzhiyun error_device:
698*4882a593Smuzhiyun ida_simple_remove(&fpga_mgr_ida, mgr->dev.id);
699*4882a593Smuzhiyun
700*4882a593Smuzhiyun return ret;
701*4882a593Smuzhiyun }
702*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(fpga_mgr_register);
703*4882a593Smuzhiyun
704*4882a593Smuzhiyun /**
705*4882a593Smuzhiyun * fpga_mgr_unregister - unregister a FPGA manager
706*4882a593Smuzhiyun * @mgr: fpga manager struct
707*4882a593Smuzhiyun *
708*4882a593Smuzhiyun * This function is intended for use in a FPGA manager driver's remove function.
709*4882a593Smuzhiyun */
fpga_mgr_unregister(struct fpga_manager * mgr)710*4882a593Smuzhiyun void fpga_mgr_unregister(struct fpga_manager *mgr)
711*4882a593Smuzhiyun {
712*4882a593Smuzhiyun dev_info(&mgr->dev, "%s %s\n", __func__, mgr->name);
713*4882a593Smuzhiyun
714*4882a593Smuzhiyun /*
715*4882a593Smuzhiyun * If the low level driver provides a method for putting fpga into
716*4882a593Smuzhiyun * a desired state upon unregister, do it.
717*4882a593Smuzhiyun */
718*4882a593Smuzhiyun if (mgr->mops->fpga_remove)
719*4882a593Smuzhiyun mgr->mops->fpga_remove(mgr);
720*4882a593Smuzhiyun
721*4882a593Smuzhiyun device_unregister(&mgr->dev);
722*4882a593Smuzhiyun }
723*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(fpga_mgr_unregister);
724*4882a593Smuzhiyun
fpga_mgr_dev_release(struct device * dev)725*4882a593Smuzhiyun static void fpga_mgr_dev_release(struct device *dev)
726*4882a593Smuzhiyun {
727*4882a593Smuzhiyun }
728*4882a593Smuzhiyun
fpga_mgr_class_init(void)729*4882a593Smuzhiyun static int __init fpga_mgr_class_init(void)
730*4882a593Smuzhiyun {
731*4882a593Smuzhiyun pr_info("FPGA manager framework\n");
732*4882a593Smuzhiyun
733*4882a593Smuzhiyun fpga_mgr_class = class_create(THIS_MODULE, "fpga_manager");
734*4882a593Smuzhiyun if (IS_ERR(fpga_mgr_class))
735*4882a593Smuzhiyun return PTR_ERR(fpga_mgr_class);
736*4882a593Smuzhiyun
737*4882a593Smuzhiyun fpga_mgr_class->dev_groups = fpga_mgr_groups;
738*4882a593Smuzhiyun fpga_mgr_class->dev_release = fpga_mgr_dev_release;
739*4882a593Smuzhiyun
740*4882a593Smuzhiyun return 0;
741*4882a593Smuzhiyun }
742*4882a593Smuzhiyun
fpga_mgr_class_exit(void)743*4882a593Smuzhiyun static void __exit fpga_mgr_class_exit(void)
744*4882a593Smuzhiyun {
745*4882a593Smuzhiyun class_destroy(fpga_mgr_class);
746*4882a593Smuzhiyun ida_destroy(&fpga_mgr_ida);
747*4882a593Smuzhiyun }
748*4882a593Smuzhiyun
749*4882a593Smuzhiyun MODULE_AUTHOR("Alan Tull <atull@kernel.org>");
750*4882a593Smuzhiyun MODULE_DESCRIPTION("FPGA manager framework");
751*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
752*4882a593Smuzhiyun
753*4882a593Smuzhiyun subsys_initcall(fpga_mgr_class_init);
754*4882a593Smuzhiyun module_exit(fpga_mgr_class_exit);
755