1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Header file for FPGA Management Engine (FME) Partial Reconfiguration Driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2017-2018 Intel Corporation, Inc. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Authors: 8*4882a593Smuzhiyun * Kang Luwei <luwei.kang@intel.com> 9*4882a593Smuzhiyun * Xiao Guangrong <guangrong.xiao@linux.intel.com> 10*4882a593Smuzhiyun * Wu Hao <hao.wu@intel.com> 11*4882a593Smuzhiyun * Joseph Grecco <joe.grecco@intel.com> 12*4882a593Smuzhiyun * Enno Luebbers <enno.luebbers@intel.com> 13*4882a593Smuzhiyun * Tim Whisonant <tim.whisonant@intel.com> 14*4882a593Smuzhiyun * Ananda Ravuri <ananda.ravuri@intel.com> 15*4882a593Smuzhiyun * Henry Mitchel <henry.mitchel@intel.com> 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #ifndef __DFL_FME_PR_H 19*4882a593Smuzhiyun #define __DFL_FME_PR_H 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #include <linux/platform_device.h> 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /** 24*4882a593Smuzhiyun * struct dfl_fme_region - FME fpga region data structure 25*4882a593Smuzhiyun * 26*4882a593Smuzhiyun * @region: platform device of the FPGA region. 27*4882a593Smuzhiyun * @node: used to link fme_region to a list. 28*4882a593Smuzhiyun * @port_id: indicate which port this region connected to. 29*4882a593Smuzhiyun */ 30*4882a593Smuzhiyun struct dfl_fme_region { 31*4882a593Smuzhiyun struct platform_device *region; 32*4882a593Smuzhiyun struct list_head node; 33*4882a593Smuzhiyun int port_id; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /** 37*4882a593Smuzhiyun * struct dfl_fme_region_pdata - platform data for FME region platform device. 38*4882a593Smuzhiyun * 39*4882a593Smuzhiyun * @mgr: platform device of the FPGA manager. 40*4882a593Smuzhiyun * @br: platform device of the FPGA bridge. 41*4882a593Smuzhiyun * @region_id: region id (same as port_id). 42*4882a593Smuzhiyun */ 43*4882a593Smuzhiyun struct dfl_fme_region_pdata { 44*4882a593Smuzhiyun struct platform_device *mgr; 45*4882a593Smuzhiyun struct platform_device *br; 46*4882a593Smuzhiyun int region_id; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /** 50*4882a593Smuzhiyun * struct dfl_fme_bridge - FME fpga bridge data structure 51*4882a593Smuzhiyun * 52*4882a593Smuzhiyun * @br: platform device of the FPGA bridge. 53*4882a593Smuzhiyun * @node: used to link fme_bridge to a list. 54*4882a593Smuzhiyun */ 55*4882a593Smuzhiyun struct dfl_fme_bridge { 56*4882a593Smuzhiyun struct platform_device *br; 57*4882a593Smuzhiyun struct list_head node; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /** 61*4882a593Smuzhiyun * struct dfl_fme_bridge_pdata - platform data for FME bridge platform device. 62*4882a593Smuzhiyun * 63*4882a593Smuzhiyun * @cdev: container device. 64*4882a593Smuzhiyun * @port_id: port id. 65*4882a593Smuzhiyun */ 66*4882a593Smuzhiyun struct dfl_fme_br_pdata { 67*4882a593Smuzhiyun struct dfl_fpga_cdev *cdev; 68*4882a593Smuzhiyun int port_id; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /** 72*4882a593Smuzhiyun * struct dfl_fme_mgr_pdata - platform data for FME manager platform device. 73*4882a593Smuzhiyun * 74*4882a593Smuzhiyun * @ioaddr: mapped io address for FME manager platform device. 75*4882a593Smuzhiyun */ 76*4882a593Smuzhiyun struct dfl_fme_mgr_pdata { 77*4882a593Smuzhiyun void __iomem *ioaddr; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define DFL_FPGA_FME_MGR "dfl-fme-mgr" 81*4882a593Smuzhiyun #define DFL_FPGA_FME_BRIDGE "dfl-fme-bridge" 82*4882a593Smuzhiyun #define DFL_FPGA_FME_REGION "dfl-fme-region" 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #endif /* __DFL_FME_PR_H */ 85