1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun# 3*4882a593Smuzhiyun# FPGA framework configuration 4*4882a593Smuzhiyun# 5*4882a593Smuzhiyun 6*4882a593Smuzhiyunmenuconfig FPGA 7*4882a593Smuzhiyun tristate "FPGA Configuration Framework" 8*4882a593Smuzhiyun help 9*4882a593Smuzhiyun Say Y here if you want support for configuring FPGAs from the 10*4882a593Smuzhiyun kernel. The FPGA framework adds a FPGA manager class and FPGA 11*4882a593Smuzhiyun manager drivers. 12*4882a593Smuzhiyun 13*4882a593Smuzhiyunif FPGA 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunconfig FPGA_MGR_SOCFPGA 16*4882a593Smuzhiyun tristate "Altera SOCFPGA FPGA Manager" 17*4882a593Smuzhiyun depends on ARCH_SOCFPGA || COMPILE_TEST 18*4882a593Smuzhiyun help 19*4882a593Smuzhiyun FPGA manager driver support for Altera SOCFPGA. 20*4882a593Smuzhiyun 21*4882a593Smuzhiyunconfig FPGA_MGR_SOCFPGA_A10 22*4882a593Smuzhiyun tristate "Altera SoCFPGA Arria10" 23*4882a593Smuzhiyun depends on ARCH_SOCFPGA || COMPILE_TEST 24*4882a593Smuzhiyun select REGMAP_MMIO 25*4882a593Smuzhiyun help 26*4882a593Smuzhiyun FPGA manager driver support for Altera Arria10 SoCFPGA. 27*4882a593Smuzhiyun 28*4882a593Smuzhiyunconfig ALTERA_PR_IP_CORE 29*4882a593Smuzhiyun tristate "Altera Partial Reconfiguration IP Core" 30*4882a593Smuzhiyun help 31*4882a593Smuzhiyun Core driver support for Altera Partial Reconfiguration IP component 32*4882a593Smuzhiyun 33*4882a593Smuzhiyunconfig ALTERA_PR_IP_CORE_PLAT 34*4882a593Smuzhiyun tristate "Platform support of Altera Partial Reconfiguration IP Core" 35*4882a593Smuzhiyun depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM 36*4882a593Smuzhiyun help 37*4882a593Smuzhiyun Platform driver support for Altera Partial Reconfiguration IP 38*4882a593Smuzhiyun component 39*4882a593Smuzhiyun 40*4882a593Smuzhiyunconfig FPGA_MGR_ALTERA_PS_SPI 41*4882a593Smuzhiyun tristate "Altera FPGA Passive Serial over SPI" 42*4882a593Smuzhiyun depends on SPI 43*4882a593Smuzhiyun select BITREVERSE 44*4882a593Smuzhiyun help 45*4882a593Smuzhiyun FPGA manager driver support for Altera Arria/Cyclone/Stratix 46*4882a593Smuzhiyun using the passive serial interface over SPI. 47*4882a593Smuzhiyun 48*4882a593Smuzhiyunconfig FPGA_MGR_ALTERA_CVP 49*4882a593Smuzhiyun tristate "Altera CvP FPGA Manager" 50*4882a593Smuzhiyun depends on PCI 51*4882a593Smuzhiyun help 52*4882a593Smuzhiyun FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V, 53*4882a593Smuzhiyun Arria 10 and Stratix10 Altera FPGAs using the CvP interface over PCIe. 54*4882a593Smuzhiyun 55*4882a593Smuzhiyunconfig FPGA_MGR_ZYNQ_FPGA 56*4882a593Smuzhiyun tristate "Xilinx Zynq FPGA" 57*4882a593Smuzhiyun depends on ARCH_ZYNQ || COMPILE_TEST 58*4882a593Smuzhiyun help 59*4882a593Smuzhiyun FPGA manager driver support for Xilinx Zynq FPGAs. 60*4882a593Smuzhiyun 61*4882a593Smuzhiyunconfig FPGA_MGR_STRATIX10_SOC 62*4882a593Smuzhiyun tristate "Intel Stratix10 SoC FPGA Manager" 63*4882a593Smuzhiyun depends on (ARCH_STRATIX10 && INTEL_STRATIX10_SERVICE) 64*4882a593Smuzhiyun help 65*4882a593Smuzhiyun FPGA manager driver support for the Intel Stratix10 SoC. 66*4882a593Smuzhiyun 67*4882a593Smuzhiyunconfig FPGA_MGR_XILINX_SPI 68*4882a593Smuzhiyun tristate "Xilinx Configuration over Slave Serial (SPI)" 69*4882a593Smuzhiyun depends on SPI 70*4882a593Smuzhiyun help 71*4882a593Smuzhiyun FPGA manager driver support for Xilinx FPGA configuration 72*4882a593Smuzhiyun over slave serial interface. 73*4882a593Smuzhiyun 74*4882a593Smuzhiyunconfig FPGA_MGR_ICE40_SPI 75*4882a593Smuzhiyun tristate "Lattice iCE40 SPI" 76*4882a593Smuzhiyun depends on OF && SPI 77*4882a593Smuzhiyun help 78*4882a593Smuzhiyun FPGA manager driver support for Lattice iCE40 FPGAs over SPI. 79*4882a593Smuzhiyun 80*4882a593Smuzhiyunconfig FPGA_MGR_MACHXO2_SPI 81*4882a593Smuzhiyun tristate "Lattice MachXO2 SPI" 82*4882a593Smuzhiyun depends on SPI 83*4882a593Smuzhiyun help 84*4882a593Smuzhiyun FPGA manager driver support for Lattice MachXO2 configuration 85*4882a593Smuzhiyun over slave SPI interface. 86*4882a593Smuzhiyun 87*4882a593Smuzhiyunconfig FPGA_MGR_TS73XX 88*4882a593Smuzhiyun tristate "Technologic Systems TS-73xx SBC FPGA Manager" 89*4882a593Smuzhiyun depends on ARCH_EP93XX && MACH_TS72XX 90*4882a593Smuzhiyun help 91*4882a593Smuzhiyun FPGA manager driver support for the Altera Cyclone II FPGA 92*4882a593Smuzhiyun present on the TS-73xx SBC boards. 93*4882a593Smuzhiyun 94*4882a593Smuzhiyunconfig FPGA_BRIDGE 95*4882a593Smuzhiyun tristate "FPGA Bridge Framework" 96*4882a593Smuzhiyun help 97*4882a593Smuzhiyun Say Y here if you want to support bridges connected between host 98*4882a593Smuzhiyun processors and FPGAs or between FPGAs. 99*4882a593Smuzhiyun 100*4882a593Smuzhiyunconfig SOCFPGA_FPGA_BRIDGE 101*4882a593Smuzhiyun tristate "Altera SoCFPGA FPGA Bridges" 102*4882a593Smuzhiyun depends on ARCH_SOCFPGA && FPGA_BRIDGE 103*4882a593Smuzhiyun help 104*4882a593Smuzhiyun Say Y to enable drivers for FPGA bridges for Altera SOCFPGA 105*4882a593Smuzhiyun devices. 106*4882a593Smuzhiyun 107*4882a593Smuzhiyunconfig ALTERA_FREEZE_BRIDGE 108*4882a593Smuzhiyun tristate "Altera FPGA Freeze Bridge" 109*4882a593Smuzhiyun depends on FPGA_BRIDGE && HAS_IOMEM 110*4882a593Smuzhiyun help 111*4882a593Smuzhiyun Say Y to enable drivers for Altera FPGA Freeze bridges. A 112*4882a593Smuzhiyun freeze bridge is a bridge that exists in the FPGA fabric to 113*4882a593Smuzhiyun isolate one region of the FPGA from the busses while that 114*4882a593Smuzhiyun region is being reprogrammed. 115*4882a593Smuzhiyun 116*4882a593Smuzhiyunconfig XILINX_PR_DECOUPLER 117*4882a593Smuzhiyun tristate "Xilinx LogiCORE PR Decoupler" 118*4882a593Smuzhiyun depends on FPGA_BRIDGE 119*4882a593Smuzhiyun depends on HAS_IOMEM 120*4882a593Smuzhiyun help 121*4882a593Smuzhiyun Say Y to enable drivers for Xilinx LogiCORE PR Decoupler. 122*4882a593Smuzhiyun The PR Decoupler exists in the FPGA fabric to isolate one 123*4882a593Smuzhiyun region of the FPGA from the busses while that region is 124*4882a593Smuzhiyun being reprogrammed during partial reconfig. 125*4882a593Smuzhiyun 126*4882a593Smuzhiyunconfig FPGA_REGION 127*4882a593Smuzhiyun tristate "FPGA Region" 128*4882a593Smuzhiyun depends on FPGA_BRIDGE 129*4882a593Smuzhiyun help 130*4882a593Smuzhiyun FPGA Region common code. A FPGA Region controls a FPGA Manager 131*4882a593Smuzhiyun and the FPGA Bridges associated with either a reconfigurable 132*4882a593Smuzhiyun region of an FPGA or a whole FPGA. 133*4882a593Smuzhiyun 134*4882a593Smuzhiyunconfig OF_FPGA_REGION 135*4882a593Smuzhiyun tristate "FPGA Region Device Tree Overlay Support" 136*4882a593Smuzhiyun depends on OF && FPGA_REGION 137*4882a593Smuzhiyun help 138*4882a593Smuzhiyun Support for loading FPGA images by applying a Device Tree 139*4882a593Smuzhiyun overlay. 140*4882a593Smuzhiyun 141*4882a593Smuzhiyunconfig FPGA_DFL 142*4882a593Smuzhiyun tristate "FPGA Device Feature List (DFL) support" 143*4882a593Smuzhiyun select FPGA_BRIDGE 144*4882a593Smuzhiyun select FPGA_REGION 145*4882a593Smuzhiyun depends on HAS_IOMEM 146*4882a593Smuzhiyun help 147*4882a593Smuzhiyun Device Feature List (DFL) defines a feature list structure that 148*4882a593Smuzhiyun creates a linked list of feature headers within the MMIO space 149*4882a593Smuzhiyun to provide an extensible way of adding features for FPGA. 150*4882a593Smuzhiyun Driver can walk through the feature headers to enumerate feature 151*4882a593Smuzhiyun devices (e.g. FPGA Management Engine, Port and Accelerator 152*4882a593Smuzhiyun Function Unit) and their private features for target FPGA devices. 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun Select this option to enable common support for Field-Programmable 155*4882a593Smuzhiyun Gate Array (FPGA) solutions which implement Device Feature List. 156*4882a593Smuzhiyun It provides enumeration APIs and feature device infrastructure. 157*4882a593Smuzhiyun 158*4882a593Smuzhiyunconfig FPGA_DFL_FME 159*4882a593Smuzhiyun tristate "FPGA DFL FME Driver" 160*4882a593Smuzhiyun depends on FPGA_DFL && HWMON && PERF_EVENTS 161*4882a593Smuzhiyun help 162*4882a593Smuzhiyun The FPGA Management Engine (FME) is a feature device implemented 163*4882a593Smuzhiyun under Device Feature List (DFL) framework. Select this option to 164*4882a593Smuzhiyun enable the platform device driver for FME which implements all 165*4882a593Smuzhiyun FPGA platform level management features. There shall be one FME 166*4882a593Smuzhiyun per DFL based FPGA device. 167*4882a593Smuzhiyun 168*4882a593Smuzhiyunconfig FPGA_DFL_FME_MGR 169*4882a593Smuzhiyun tristate "FPGA DFL FME Manager Driver" 170*4882a593Smuzhiyun depends on FPGA_DFL_FME && HAS_IOMEM 171*4882a593Smuzhiyun help 172*4882a593Smuzhiyun Say Y to enable FPGA Manager driver for FPGA Management Engine. 173*4882a593Smuzhiyun 174*4882a593Smuzhiyunconfig FPGA_DFL_FME_BRIDGE 175*4882a593Smuzhiyun tristate "FPGA DFL FME Bridge Driver" 176*4882a593Smuzhiyun depends on FPGA_DFL_FME && HAS_IOMEM 177*4882a593Smuzhiyun help 178*4882a593Smuzhiyun Say Y to enable FPGA Bridge driver for FPGA Management Engine. 179*4882a593Smuzhiyun 180*4882a593Smuzhiyunconfig FPGA_DFL_FME_REGION 181*4882a593Smuzhiyun tristate "FPGA DFL FME Region Driver" 182*4882a593Smuzhiyun depends on FPGA_DFL_FME && HAS_IOMEM 183*4882a593Smuzhiyun help 184*4882a593Smuzhiyun Say Y to enable FPGA Region driver for FPGA Management Engine. 185*4882a593Smuzhiyun 186*4882a593Smuzhiyunconfig FPGA_DFL_AFU 187*4882a593Smuzhiyun tristate "FPGA DFL AFU Driver" 188*4882a593Smuzhiyun depends on FPGA_DFL 189*4882a593Smuzhiyun help 190*4882a593Smuzhiyun This is the driver for FPGA Accelerated Function Unit (AFU) which 191*4882a593Smuzhiyun implements AFU and Port management features. A User AFU connects 192*4882a593Smuzhiyun to the FPGA infrastructure via a Port. There may be more than one 193*4882a593Smuzhiyun Port/AFU per DFL based FPGA device. 194*4882a593Smuzhiyun 195*4882a593Smuzhiyunconfig FPGA_DFL_PCI 196*4882a593Smuzhiyun tristate "FPGA DFL PCIe Device Driver" 197*4882a593Smuzhiyun depends on PCI && FPGA_DFL 198*4882a593Smuzhiyun help 199*4882a593Smuzhiyun Select this option to enable PCIe driver for PCIe-based 200*4882a593Smuzhiyun Field-Programmable Gate Array (FPGA) solutions which implement 201*4882a593Smuzhiyun the Device Feature List (DFL). This driver provides interfaces 202*4882a593Smuzhiyun for userspace applications to configure, enumerate, open and access 203*4882a593Smuzhiyun FPGA accelerators on the FPGA DFL devices, enables system level 204*4882a593Smuzhiyun management functions such as FPGA partial reconfiguration, power 205*4882a593Smuzhiyun management and virtualization with DFL framework and DFL feature 206*4882a593Smuzhiyun device drivers. 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun To compile this as a module, choose M here. 209*4882a593Smuzhiyun 210*4882a593Smuzhiyunconfig FPGA_MGR_ZYNQMP_FPGA 211*4882a593Smuzhiyun tristate "Xilinx ZynqMP FPGA" 212*4882a593Smuzhiyun depends on ZYNQMP_FIRMWARE || (!ZYNQMP_FIRMWARE && COMPILE_TEST) 213*4882a593Smuzhiyun help 214*4882a593Smuzhiyun FPGA manager driver support for Xilinx ZynqMP FPGAs. 215*4882a593Smuzhiyun This driver uses the processor configuration port(PCAP) 216*4882a593Smuzhiyun to configure the programmable logic(PL) through PS 217*4882a593Smuzhiyun on ZynqMP SoC. 218*4882a593Smuzhiyun 219*4882a593Smuzhiyunendif # FPGA 220