1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Trusted Foundations support for ARM CPUs
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2013, NVIDIA Corporation.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/init.h>
10*4882a593Smuzhiyun #include <linux/of.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/firmware/trusted_foundations.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <asm/firmware.h>
15*4882a593Smuzhiyun #include <asm/hardware/cache-l2x0.h>
16*4882a593Smuzhiyun #include <asm/outercache.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define TF_CACHE_MAINT 0xfffff100
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define TF_CACHE_ENABLE 1
21*4882a593Smuzhiyun #define TF_CACHE_DISABLE 2
22*4882a593Smuzhiyun #define TF_CACHE_REENABLE 4
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define TF_CPU_PM 0xfffffffc
27*4882a593Smuzhiyun #define TF_CPU_PM_S3 0xffffffe3
28*4882a593Smuzhiyun #define TF_CPU_PM_S2 0xffffffe6
29*4882a593Smuzhiyun #define TF_CPU_PM_S2_NO_MC_CLK 0xffffffe5
30*4882a593Smuzhiyun #define TF_CPU_PM_S1 0xffffffe4
31*4882a593Smuzhiyun #define TF_CPU_PM_S1_NOFLUSH_L2 0xffffffe7
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun static unsigned long tf_idle_mode = TF_PM_MODE_NONE;
34*4882a593Smuzhiyun static unsigned long cpu_boot_addr;
35*4882a593Smuzhiyun
tf_generic_smc(u32 type,u32 arg1,u32 arg2)36*4882a593Smuzhiyun static void tf_generic_smc(u32 type, u32 arg1, u32 arg2)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun register u32 r0 asm("r0") = type;
39*4882a593Smuzhiyun register u32 r1 asm("r1") = arg1;
40*4882a593Smuzhiyun register u32 r2 asm("r2") = arg2;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun asm volatile(
43*4882a593Smuzhiyun ".arch_extension sec\n\t"
44*4882a593Smuzhiyun "stmfd sp!, {r4 - r11}\n\t"
45*4882a593Smuzhiyun __asmeq("%0", "r0")
46*4882a593Smuzhiyun __asmeq("%1", "r1")
47*4882a593Smuzhiyun __asmeq("%2", "r2")
48*4882a593Smuzhiyun "mov r3, #0\n\t"
49*4882a593Smuzhiyun "mov r4, #0\n\t"
50*4882a593Smuzhiyun "smc #0\n\t"
51*4882a593Smuzhiyun "ldmfd sp!, {r4 - r11}\n\t"
52*4882a593Smuzhiyun :
53*4882a593Smuzhiyun : "r" (r0), "r" (r1), "r" (r2)
54*4882a593Smuzhiyun : "memory", "r3", "r12", "lr");
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
tf_set_cpu_boot_addr(int cpu,unsigned long boot_addr)57*4882a593Smuzhiyun static int tf_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun cpu_boot_addr = boot_addr;
60*4882a593Smuzhiyun tf_generic_smc(TF_SET_CPU_BOOT_ADDR_SMC, cpu_boot_addr, 0);
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun return 0;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
tf_prepare_idle(unsigned long mode)65*4882a593Smuzhiyun static int tf_prepare_idle(unsigned long mode)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun switch (mode) {
68*4882a593Smuzhiyun case TF_PM_MODE_LP0:
69*4882a593Smuzhiyun tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S3, cpu_boot_addr);
70*4882a593Smuzhiyun break;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun case TF_PM_MODE_LP1:
73*4882a593Smuzhiyun tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S2, cpu_boot_addr);
74*4882a593Smuzhiyun break;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun case TF_PM_MODE_LP1_NO_MC_CLK:
77*4882a593Smuzhiyun tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S2_NO_MC_CLK,
78*4882a593Smuzhiyun cpu_boot_addr);
79*4882a593Smuzhiyun break;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun case TF_PM_MODE_LP2:
82*4882a593Smuzhiyun tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S1, cpu_boot_addr);
83*4882a593Smuzhiyun break;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun case TF_PM_MODE_LP2_NOFLUSH_L2:
86*4882a593Smuzhiyun tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S1_NOFLUSH_L2,
87*4882a593Smuzhiyun cpu_boot_addr);
88*4882a593Smuzhiyun break;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun case TF_PM_MODE_NONE:
91*4882a593Smuzhiyun break;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun default:
94*4882a593Smuzhiyun return -EINVAL;
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun tf_idle_mode = mode;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun return 0;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun #ifdef CONFIG_CACHE_L2X0
tf_cache_write_sec(unsigned long val,unsigned int reg)103*4882a593Smuzhiyun static void tf_cache_write_sec(unsigned long val, unsigned int reg)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun u32 enable_op, l2x0_way_mask = 0xff;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun switch (reg) {
108*4882a593Smuzhiyun case L2X0_CTRL:
109*4882a593Smuzhiyun if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_ASSOCIATIVITY_16)
110*4882a593Smuzhiyun l2x0_way_mask = 0xffff;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun switch (tf_idle_mode) {
113*4882a593Smuzhiyun case TF_PM_MODE_LP2:
114*4882a593Smuzhiyun enable_op = TF_CACHE_REENABLE;
115*4882a593Smuzhiyun break;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun default:
118*4882a593Smuzhiyun enable_op = TF_CACHE_ENABLE;
119*4882a593Smuzhiyun break;
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun if (val == L2X0_CTRL_EN)
123*4882a593Smuzhiyun tf_generic_smc(TF_CACHE_MAINT, enable_op,
124*4882a593Smuzhiyun l2x0_saved_regs.aux_ctrl);
125*4882a593Smuzhiyun else
126*4882a593Smuzhiyun tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_DISABLE,
127*4882a593Smuzhiyun l2x0_way_mask);
128*4882a593Smuzhiyun break;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun default:
131*4882a593Smuzhiyun break;
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
tf_init_cache(void)135*4882a593Smuzhiyun static int tf_init_cache(void)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun outer_cache.write_sec = tf_cache_write_sec;
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun return 0;
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun #endif /* CONFIG_CACHE_L2X0 */
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun static const struct firmware_ops trusted_foundations_ops = {
144*4882a593Smuzhiyun .set_cpu_boot_addr = tf_set_cpu_boot_addr,
145*4882a593Smuzhiyun .prepare_idle = tf_prepare_idle,
146*4882a593Smuzhiyun #ifdef CONFIG_CACHE_L2X0
147*4882a593Smuzhiyun .l2x0_init = tf_init_cache,
148*4882a593Smuzhiyun #endif
149*4882a593Smuzhiyun };
150*4882a593Smuzhiyun
register_trusted_foundations(struct trusted_foundations_platform_data * pd)151*4882a593Smuzhiyun void register_trusted_foundations(struct trusted_foundations_platform_data *pd)
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun /*
154*4882a593Smuzhiyun * we are not using version information for now since currently
155*4882a593Smuzhiyun * supported SMCs are compatible with all TF releases
156*4882a593Smuzhiyun */
157*4882a593Smuzhiyun register_firmware_ops(&trusted_foundations_ops);
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun
of_register_trusted_foundations(void)160*4882a593Smuzhiyun void of_register_trusted_foundations(void)
161*4882a593Smuzhiyun {
162*4882a593Smuzhiyun struct device_node *node;
163*4882a593Smuzhiyun struct trusted_foundations_platform_data pdata;
164*4882a593Smuzhiyun int err;
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun node = of_find_compatible_node(NULL, NULL, "tlm,trusted-foundations");
167*4882a593Smuzhiyun if (!node)
168*4882a593Smuzhiyun return;
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun err = of_property_read_u32(node, "tlm,version-major",
171*4882a593Smuzhiyun &pdata.version_major);
172*4882a593Smuzhiyun if (err != 0)
173*4882a593Smuzhiyun panic("Trusted Foundation: missing version-major property\n");
174*4882a593Smuzhiyun err = of_property_read_u32(node, "tlm,version-minor",
175*4882a593Smuzhiyun &pdata.version_minor);
176*4882a593Smuzhiyun if (err != 0)
177*4882a593Smuzhiyun panic("Trusted Foundation: missing version-minor property\n");
178*4882a593Smuzhiyun register_trusted_foundations(&pdata);
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun
trusted_foundations_registered(void)181*4882a593Smuzhiyun bool trusted_foundations_registered(void)
182*4882a593Smuzhiyun {
183*4882a593Smuzhiyun return firmware_ops == &trusted_foundations_ops;
184*4882a593Smuzhiyun }
185