1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2018, NVIDIA CORPORATION.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/interrupt.h>
7*4882a593Smuzhiyun #include <linux/irq.h>
8*4882a593Smuzhiyun #include <linux/io.h>
9*4882a593Smuzhiyun #include <linux/of.h>
10*4882a593Smuzhiyun #include <linux/platform_device.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <soc/tegra/bpmp.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include "bpmp-private.h"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define TRIGGER_OFFSET 0x000
17*4882a593Smuzhiyun #define RESULT_OFFSET(id) (0xc00 + id * 4)
18*4882a593Smuzhiyun #define TRIGGER_ID_SHIFT 16
19*4882a593Smuzhiyun #define TRIGGER_CMD_GET 4
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define STA_OFFSET 0
22*4882a593Smuzhiyun #define SET_OFFSET 4
23*4882a593Smuzhiyun #define CLR_OFFSET 8
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define CH_MASK(ch) (0x3 << ((ch) * 2))
26*4882a593Smuzhiyun #define SL_SIGL(ch) (0x0 << ((ch) * 2))
27*4882a593Smuzhiyun #define SL_QUED(ch) (0x1 << ((ch) * 2))
28*4882a593Smuzhiyun #define MA_FREE(ch) (0x2 << ((ch) * 2))
29*4882a593Smuzhiyun #define MA_ACKD(ch) (0x3 << ((ch) * 2))
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun struct tegra210_bpmp {
32*4882a593Smuzhiyun void __iomem *atomics;
33*4882a593Smuzhiyun void __iomem *arb_sema;
34*4882a593Smuzhiyun struct irq_data *tx_irq_data;
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun
bpmp_channel_status(struct tegra_bpmp * bpmp,unsigned int index)37*4882a593Smuzhiyun static u32 bpmp_channel_status(struct tegra_bpmp *bpmp, unsigned int index)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun struct tegra210_bpmp *priv = bpmp->priv;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun return __raw_readl(priv->arb_sema + STA_OFFSET) & CH_MASK(index);
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
tegra210_bpmp_is_response_ready(struct tegra_bpmp_channel * channel)44*4882a593Smuzhiyun static bool tegra210_bpmp_is_response_ready(struct tegra_bpmp_channel *channel)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun unsigned int index = channel->index;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun return bpmp_channel_status(channel->bpmp, index) == MA_ACKD(index);
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
tegra210_bpmp_is_request_ready(struct tegra_bpmp_channel * channel)51*4882a593Smuzhiyun static bool tegra210_bpmp_is_request_ready(struct tegra_bpmp_channel *channel)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun unsigned int index = channel->index;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun return bpmp_channel_status(channel->bpmp, index) == SL_SIGL(index);
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun static bool
tegra210_bpmp_is_request_channel_free(struct tegra_bpmp_channel * channel)59*4882a593Smuzhiyun tegra210_bpmp_is_request_channel_free(struct tegra_bpmp_channel *channel)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun unsigned int index = channel->index;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun return bpmp_channel_status(channel->bpmp, index) == MA_FREE(index);
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun static bool
tegra210_bpmp_is_response_channel_free(struct tegra_bpmp_channel * channel)67*4882a593Smuzhiyun tegra210_bpmp_is_response_channel_free(struct tegra_bpmp_channel *channel)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun unsigned int index = channel->index;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun return bpmp_channel_status(channel->bpmp, index) == SL_QUED(index);
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
tegra210_bpmp_post_request(struct tegra_bpmp_channel * channel)74*4882a593Smuzhiyun static int tegra210_bpmp_post_request(struct tegra_bpmp_channel *channel)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun struct tegra210_bpmp *priv = channel->bpmp->priv;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun __raw_writel(CH_MASK(channel->index), priv->arb_sema + CLR_OFFSET);
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun return 0;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
tegra210_bpmp_post_response(struct tegra_bpmp_channel * channel)83*4882a593Smuzhiyun static int tegra210_bpmp_post_response(struct tegra_bpmp_channel *channel)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun struct tegra210_bpmp *priv = channel->bpmp->priv;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun __raw_writel(MA_ACKD(channel->index), priv->arb_sema + SET_OFFSET);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun return 0;
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
tegra210_bpmp_ack_response(struct tegra_bpmp_channel * channel)92*4882a593Smuzhiyun static int tegra210_bpmp_ack_response(struct tegra_bpmp_channel *channel)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun struct tegra210_bpmp *priv = channel->bpmp->priv;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun __raw_writel(MA_ACKD(channel->index) ^ MA_FREE(channel->index),
97*4882a593Smuzhiyun priv->arb_sema + CLR_OFFSET);
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun return 0;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
tegra210_bpmp_ack_request(struct tegra_bpmp_channel * channel)102*4882a593Smuzhiyun static int tegra210_bpmp_ack_request(struct tegra_bpmp_channel *channel)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun struct tegra210_bpmp *priv = channel->bpmp->priv;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun __raw_writel(SL_QUED(channel->index), priv->arb_sema + SET_OFFSET);
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun return 0;
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun
tegra210_bpmp_ring_doorbell(struct tegra_bpmp * bpmp)111*4882a593Smuzhiyun static int tegra210_bpmp_ring_doorbell(struct tegra_bpmp *bpmp)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun struct tegra210_bpmp *priv = bpmp->priv;
114*4882a593Smuzhiyun struct irq_data *irq_data = priv->tx_irq_data;
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun /*
117*4882a593Smuzhiyun * Tegra Legacy Interrupt Controller (LIC) is used to notify BPMP of
118*4882a593Smuzhiyun * available messages
119*4882a593Smuzhiyun */
120*4882a593Smuzhiyun if (irq_data->chip->irq_retrigger)
121*4882a593Smuzhiyun return irq_data->chip->irq_retrigger(irq_data);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun return -EINVAL;
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun
rx_irq(int irq,void * data)126*4882a593Smuzhiyun static irqreturn_t rx_irq(int irq, void *data)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun struct tegra_bpmp *bpmp = data;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun tegra_bpmp_handle_rx(bpmp);
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun return IRQ_HANDLED;
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
tegra210_bpmp_channel_init(struct tegra_bpmp_channel * channel,struct tegra_bpmp * bpmp,unsigned int index)135*4882a593Smuzhiyun static int tegra210_bpmp_channel_init(struct tegra_bpmp_channel *channel,
136*4882a593Smuzhiyun struct tegra_bpmp *bpmp,
137*4882a593Smuzhiyun unsigned int index)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun struct tegra210_bpmp *priv = bpmp->priv;
140*4882a593Smuzhiyun u32 address;
141*4882a593Smuzhiyun void *p;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun /* Retrieve channel base address from BPMP */
144*4882a593Smuzhiyun writel(index << TRIGGER_ID_SHIFT | TRIGGER_CMD_GET,
145*4882a593Smuzhiyun priv->atomics + TRIGGER_OFFSET);
146*4882a593Smuzhiyun address = readl(priv->atomics + RESULT_OFFSET(index));
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun p = devm_ioremap(bpmp->dev, address, 0x80);
149*4882a593Smuzhiyun if (!p)
150*4882a593Smuzhiyun return -ENOMEM;
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun channel->ib = p;
153*4882a593Smuzhiyun channel->ob = p;
154*4882a593Smuzhiyun channel->index = index;
155*4882a593Smuzhiyun init_completion(&channel->completion);
156*4882a593Smuzhiyun channel->bpmp = bpmp;
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun return 0;
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun
tegra210_bpmp_init(struct tegra_bpmp * bpmp)161*4882a593Smuzhiyun static int tegra210_bpmp_init(struct tegra_bpmp *bpmp)
162*4882a593Smuzhiyun {
163*4882a593Smuzhiyun struct platform_device *pdev = to_platform_device(bpmp->dev);
164*4882a593Smuzhiyun struct tegra210_bpmp *priv;
165*4882a593Smuzhiyun struct resource *res;
166*4882a593Smuzhiyun unsigned int i;
167*4882a593Smuzhiyun int err;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
170*4882a593Smuzhiyun if (!priv)
171*4882a593Smuzhiyun return -ENOMEM;
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun bpmp->priv = priv;
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
176*4882a593Smuzhiyun priv->atomics = devm_ioremap_resource(&pdev->dev, res);
177*4882a593Smuzhiyun if (IS_ERR(priv->atomics))
178*4882a593Smuzhiyun return PTR_ERR(priv->atomics);
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
181*4882a593Smuzhiyun priv->arb_sema = devm_ioremap_resource(&pdev->dev, res);
182*4882a593Smuzhiyun if (IS_ERR(priv->arb_sema))
183*4882a593Smuzhiyun return PTR_ERR(priv->arb_sema);
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun err = tegra210_bpmp_channel_init(bpmp->tx_channel, bpmp,
186*4882a593Smuzhiyun bpmp->soc->channels.cpu_tx.offset);
187*4882a593Smuzhiyun if (err < 0)
188*4882a593Smuzhiyun return err;
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun err = tegra210_bpmp_channel_init(bpmp->rx_channel, bpmp,
191*4882a593Smuzhiyun bpmp->soc->channels.cpu_rx.offset);
192*4882a593Smuzhiyun if (err < 0)
193*4882a593Smuzhiyun return err;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun for (i = 0; i < bpmp->threaded.count; i++) {
196*4882a593Smuzhiyun unsigned int index = bpmp->soc->channels.thread.offset + i;
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun err = tegra210_bpmp_channel_init(&bpmp->threaded_channels[i],
199*4882a593Smuzhiyun bpmp, index);
200*4882a593Smuzhiyun if (err < 0)
201*4882a593Smuzhiyun return err;
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun err = platform_get_irq_byname(pdev, "tx");
205*4882a593Smuzhiyun if (err < 0) {
206*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to get TX IRQ: %d\n", err);
207*4882a593Smuzhiyun return err;
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun priv->tx_irq_data = irq_get_irq_data(err);
211*4882a593Smuzhiyun if (!priv->tx_irq_data) {
212*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to get IRQ data for TX IRQ\n");
213*4882a593Smuzhiyun return -ENOENT;
214*4882a593Smuzhiyun }
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun err = platform_get_irq_byname(pdev, "rx");
217*4882a593Smuzhiyun if (err < 0) {
218*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to get rx IRQ: %d\n", err);
219*4882a593Smuzhiyun return err;
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun err = devm_request_irq(&pdev->dev, err, rx_irq,
223*4882a593Smuzhiyun IRQF_NO_SUSPEND, dev_name(&pdev->dev), bpmp);
224*4882a593Smuzhiyun if (err < 0) {
225*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
226*4882a593Smuzhiyun return err;
227*4882a593Smuzhiyun }
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun return 0;
230*4882a593Smuzhiyun }
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun const struct tegra_bpmp_ops tegra210_bpmp_ops = {
233*4882a593Smuzhiyun .init = tegra210_bpmp_init,
234*4882a593Smuzhiyun .is_response_ready = tegra210_bpmp_is_response_ready,
235*4882a593Smuzhiyun .is_request_ready = tegra210_bpmp_is_request_ready,
236*4882a593Smuzhiyun .ack_response = tegra210_bpmp_ack_response,
237*4882a593Smuzhiyun .ack_request = tegra210_bpmp_ack_request,
238*4882a593Smuzhiyun .is_response_channel_free = tegra210_bpmp_is_response_channel_free,
239*4882a593Smuzhiyun .is_request_channel_free = tegra210_bpmp_is_request_channel_free,
240*4882a593Smuzhiyun .post_response = tegra210_bpmp_post_response,
241*4882a593Smuzhiyun .post_request = tegra210_bpmp_post_request,
242*4882a593Smuzhiyun .ring_doorbell = tegra210_bpmp_ring_doorbell,
243*4882a593Smuzhiyun };
244