1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /* Copyright (c) 2015,2019 The Linux Foundation. All rights reserved.
3*4882a593Smuzhiyun */
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun #include <linux/io.h>
6*4882a593Smuzhiyun #include <linux/errno.h>
7*4882a593Smuzhiyun #include <linux/delay.h>
8*4882a593Smuzhiyun #include <linux/mutex.h>
9*4882a593Smuzhiyun #include <linux/slab.h>
10*4882a593Smuzhiyun #include <linux/types.h>
11*4882a593Smuzhiyun #include <linux/qcom_scm.h>
12*4882a593Smuzhiyun #include <linux/arm-smccc.h>
13*4882a593Smuzhiyun #include <linux/dma-mapping.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include "qcom_scm.h"
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun /**
18*4882a593Smuzhiyun * struct arm_smccc_args
19*4882a593Smuzhiyun * @args: The array of values used in registers in smc instruction
20*4882a593Smuzhiyun */
21*4882a593Smuzhiyun struct arm_smccc_args {
22*4882a593Smuzhiyun unsigned long args[8];
23*4882a593Smuzhiyun };
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun static DEFINE_MUTEX(qcom_scm_lock);
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define QCOM_SCM_EBUSY_WAIT_MS 30
28*4882a593Smuzhiyun #define QCOM_SCM_EBUSY_MAX_RETRY 20
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #define SCM_SMC_N_REG_ARGS 4
31*4882a593Smuzhiyun #define SCM_SMC_FIRST_EXT_IDX (SCM_SMC_N_REG_ARGS - 1)
32*4882a593Smuzhiyun #define SCM_SMC_N_EXT_ARGS (MAX_QCOM_SCM_ARGS - SCM_SMC_N_REG_ARGS + 1)
33*4882a593Smuzhiyun #define SCM_SMC_FIRST_REG_IDX 2
34*4882a593Smuzhiyun #define SCM_SMC_LAST_REG_IDX (SCM_SMC_FIRST_REG_IDX + SCM_SMC_N_REG_ARGS - 1)
35*4882a593Smuzhiyun
__scm_smc_do_quirk(const struct arm_smccc_args * smc,struct arm_smccc_res * res)36*4882a593Smuzhiyun static void __scm_smc_do_quirk(const struct arm_smccc_args *smc,
37*4882a593Smuzhiyun struct arm_smccc_res *res)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun unsigned long a0 = smc->args[0];
40*4882a593Smuzhiyun struct arm_smccc_quirk quirk = { .id = ARM_SMCCC_QUIRK_QCOM_A6 };
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun quirk.state.a6 = 0;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun do {
45*4882a593Smuzhiyun arm_smccc_smc_quirk(a0, smc->args[1], smc->args[2],
46*4882a593Smuzhiyun smc->args[3], smc->args[4], smc->args[5],
47*4882a593Smuzhiyun quirk.state.a6, smc->args[7], res, &quirk);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun if (res->a0 == QCOM_SCM_INTERRUPTED)
50*4882a593Smuzhiyun a0 = res->a0;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun } while (res->a0 == QCOM_SCM_INTERRUPTED);
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
__scm_smc_do(const struct arm_smccc_args * smc,struct arm_smccc_res * res,bool atomic)55*4882a593Smuzhiyun static void __scm_smc_do(const struct arm_smccc_args *smc,
56*4882a593Smuzhiyun struct arm_smccc_res *res, bool atomic)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun int retry_count = 0;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun if (atomic) {
61*4882a593Smuzhiyun __scm_smc_do_quirk(smc, res);
62*4882a593Smuzhiyun return;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun do {
66*4882a593Smuzhiyun mutex_lock(&qcom_scm_lock);
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun __scm_smc_do_quirk(smc, res);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun mutex_unlock(&qcom_scm_lock);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun if (res->a0 == QCOM_SCM_V2_EBUSY) {
73*4882a593Smuzhiyun if (retry_count++ > QCOM_SCM_EBUSY_MAX_RETRY)
74*4882a593Smuzhiyun break;
75*4882a593Smuzhiyun msleep(QCOM_SCM_EBUSY_WAIT_MS);
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun } while (res->a0 == QCOM_SCM_V2_EBUSY);
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun
__scm_smc_call(struct device * dev,const struct qcom_scm_desc * desc,enum qcom_scm_convention qcom_convention,struct qcom_scm_res * res,bool atomic)81*4882a593Smuzhiyun int __scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,
82*4882a593Smuzhiyun enum qcom_scm_convention qcom_convention,
83*4882a593Smuzhiyun struct qcom_scm_res *res, bool atomic)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun int arglen = desc->arginfo & 0xf;
86*4882a593Smuzhiyun int i;
87*4882a593Smuzhiyun dma_addr_t args_phys = 0;
88*4882a593Smuzhiyun void *args_virt = NULL;
89*4882a593Smuzhiyun size_t alloc_len;
90*4882a593Smuzhiyun gfp_t flag = atomic ? GFP_ATOMIC : GFP_KERNEL;
91*4882a593Smuzhiyun u32 smccc_call_type = atomic ? ARM_SMCCC_FAST_CALL : ARM_SMCCC_STD_CALL;
92*4882a593Smuzhiyun u32 qcom_smccc_convention = (qcom_convention == SMC_CONVENTION_ARM_32) ?
93*4882a593Smuzhiyun ARM_SMCCC_SMC_32 : ARM_SMCCC_SMC_64;
94*4882a593Smuzhiyun struct arm_smccc_res smc_res;
95*4882a593Smuzhiyun struct arm_smccc_args smc = {0};
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun smc.args[0] = ARM_SMCCC_CALL_VAL(
98*4882a593Smuzhiyun smccc_call_type,
99*4882a593Smuzhiyun qcom_smccc_convention,
100*4882a593Smuzhiyun desc->owner,
101*4882a593Smuzhiyun SCM_SMC_FNID(desc->svc, desc->cmd));
102*4882a593Smuzhiyun smc.args[1] = desc->arginfo;
103*4882a593Smuzhiyun for (i = 0; i < SCM_SMC_N_REG_ARGS; i++)
104*4882a593Smuzhiyun smc.args[i + SCM_SMC_FIRST_REG_IDX] = desc->args[i];
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun if (unlikely(arglen > SCM_SMC_N_REG_ARGS)) {
107*4882a593Smuzhiyun alloc_len = SCM_SMC_N_EXT_ARGS * sizeof(u64);
108*4882a593Smuzhiyun args_virt = kzalloc(PAGE_ALIGN(alloc_len), flag);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun if (!args_virt)
111*4882a593Smuzhiyun return -ENOMEM;
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun if (qcom_smccc_convention == ARM_SMCCC_SMC_32) {
114*4882a593Smuzhiyun __le32 *args = args_virt;
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun for (i = 0; i < SCM_SMC_N_EXT_ARGS; i++)
117*4882a593Smuzhiyun args[i] = cpu_to_le32(desc->args[i +
118*4882a593Smuzhiyun SCM_SMC_FIRST_EXT_IDX]);
119*4882a593Smuzhiyun } else {
120*4882a593Smuzhiyun __le64 *args = args_virt;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun for (i = 0; i < SCM_SMC_N_EXT_ARGS; i++)
123*4882a593Smuzhiyun args[i] = cpu_to_le64(desc->args[i +
124*4882a593Smuzhiyun SCM_SMC_FIRST_EXT_IDX]);
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun args_phys = dma_map_single(dev, args_virt, alloc_len,
128*4882a593Smuzhiyun DMA_TO_DEVICE);
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun if (dma_mapping_error(dev, args_phys)) {
131*4882a593Smuzhiyun kfree(args_virt);
132*4882a593Smuzhiyun return -ENOMEM;
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun smc.args[SCM_SMC_LAST_REG_IDX] = args_phys;
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun __scm_smc_do(&smc, &smc_res, atomic);
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun if (args_virt) {
141*4882a593Smuzhiyun dma_unmap_single(dev, args_phys, alloc_len, DMA_TO_DEVICE);
142*4882a593Smuzhiyun kfree(args_virt);
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun if (res) {
146*4882a593Smuzhiyun res->result[0] = smc_res.a1;
147*4882a593Smuzhiyun res->result[1] = smc_res.a2;
148*4882a593Smuzhiyun res->result[2] = smc_res.a3;
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun return (long)smc_res.a0 ? qcom_scm_remap_error(smc_res.a0) : 0;
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun }
154