1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _FIREWIRE_OHCI_H 3*4882a593Smuzhiyun #define _FIREWIRE_OHCI_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* OHCI register map */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #define OHCI1394_Version 0x000 8*4882a593Smuzhiyun #define OHCI1394_GUID_ROM 0x004 9*4882a593Smuzhiyun #define OHCI1394_ATRetries 0x008 10*4882a593Smuzhiyun #define OHCI1394_CSRData 0x00C 11*4882a593Smuzhiyun #define OHCI1394_CSRCompareData 0x010 12*4882a593Smuzhiyun #define OHCI1394_CSRControl 0x014 13*4882a593Smuzhiyun #define OHCI1394_ConfigROMhdr 0x018 14*4882a593Smuzhiyun #define OHCI1394_BusID 0x01C 15*4882a593Smuzhiyun #define OHCI1394_BusOptions 0x020 16*4882a593Smuzhiyun #define OHCI1394_GUIDHi 0x024 17*4882a593Smuzhiyun #define OHCI1394_GUIDLo 0x028 18*4882a593Smuzhiyun #define OHCI1394_ConfigROMmap 0x034 19*4882a593Smuzhiyun #define OHCI1394_PostedWriteAddressLo 0x038 20*4882a593Smuzhiyun #define OHCI1394_PostedWriteAddressHi 0x03C 21*4882a593Smuzhiyun #define OHCI1394_VendorID 0x040 22*4882a593Smuzhiyun #define OHCI1394_HCControlSet 0x050 23*4882a593Smuzhiyun #define OHCI1394_HCControlClear 0x054 24*4882a593Smuzhiyun #define OHCI1394_HCControl_BIBimageValid 0x80000000 25*4882a593Smuzhiyun #define OHCI1394_HCControl_noByteSwapData 0x40000000 26*4882a593Smuzhiyun #define OHCI1394_HCControl_programPhyEnable 0x00800000 27*4882a593Smuzhiyun #define OHCI1394_HCControl_aPhyEnhanceEnable 0x00400000 28*4882a593Smuzhiyun #define OHCI1394_HCControl_LPS 0x00080000 29*4882a593Smuzhiyun #define OHCI1394_HCControl_postedWriteEnable 0x00040000 30*4882a593Smuzhiyun #define OHCI1394_HCControl_linkEnable 0x00020000 31*4882a593Smuzhiyun #define OHCI1394_HCControl_softReset 0x00010000 32*4882a593Smuzhiyun #define OHCI1394_SelfIDBuffer 0x064 33*4882a593Smuzhiyun #define OHCI1394_SelfIDCount 0x068 34*4882a593Smuzhiyun #define OHCI1394_SelfIDCount_selfIDError 0x80000000 35*4882a593Smuzhiyun #define OHCI1394_IRMultiChanMaskHiSet 0x070 36*4882a593Smuzhiyun #define OHCI1394_IRMultiChanMaskHiClear 0x074 37*4882a593Smuzhiyun #define OHCI1394_IRMultiChanMaskLoSet 0x078 38*4882a593Smuzhiyun #define OHCI1394_IRMultiChanMaskLoClear 0x07C 39*4882a593Smuzhiyun #define OHCI1394_IntEventSet 0x080 40*4882a593Smuzhiyun #define OHCI1394_IntEventClear 0x084 41*4882a593Smuzhiyun #define OHCI1394_IntMaskSet 0x088 42*4882a593Smuzhiyun #define OHCI1394_IntMaskClear 0x08C 43*4882a593Smuzhiyun #define OHCI1394_IsoXmitIntEventSet 0x090 44*4882a593Smuzhiyun #define OHCI1394_IsoXmitIntEventClear 0x094 45*4882a593Smuzhiyun #define OHCI1394_IsoXmitIntMaskSet 0x098 46*4882a593Smuzhiyun #define OHCI1394_IsoXmitIntMaskClear 0x09C 47*4882a593Smuzhiyun #define OHCI1394_IsoRecvIntEventSet 0x0A0 48*4882a593Smuzhiyun #define OHCI1394_IsoRecvIntEventClear 0x0A4 49*4882a593Smuzhiyun #define OHCI1394_IsoRecvIntMaskSet 0x0A8 50*4882a593Smuzhiyun #define OHCI1394_IsoRecvIntMaskClear 0x0AC 51*4882a593Smuzhiyun #define OHCI1394_InitialBandwidthAvailable 0x0B0 52*4882a593Smuzhiyun #define OHCI1394_InitialChannelsAvailableHi 0x0B4 53*4882a593Smuzhiyun #define OHCI1394_InitialChannelsAvailableLo 0x0B8 54*4882a593Smuzhiyun #define OHCI1394_FairnessControl 0x0DC 55*4882a593Smuzhiyun #define OHCI1394_LinkControlSet 0x0E0 56*4882a593Smuzhiyun #define OHCI1394_LinkControlClear 0x0E4 57*4882a593Smuzhiyun #define OHCI1394_LinkControl_rcvSelfID (1 << 9) 58*4882a593Smuzhiyun #define OHCI1394_LinkControl_rcvPhyPkt (1 << 10) 59*4882a593Smuzhiyun #define OHCI1394_LinkControl_cycleTimerEnable (1 << 20) 60*4882a593Smuzhiyun #define OHCI1394_LinkControl_cycleMaster (1 << 21) 61*4882a593Smuzhiyun #define OHCI1394_LinkControl_cycleSource (1 << 22) 62*4882a593Smuzhiyun #define OHCI1394_NodeID 0x0E8 63*4882a593Smuzhiyun #define OHCI1394_NodeID_idValid 0x80000000 64*4882a593Smuzhiyun #define OHCI1394_NodeID_root 0x40000000 65*4882a593Smuzhiyun #define OHCI1394_NodeID_nodeNumber 0x0000003f 66*4882a593Smuzhiyun #define OHCI1394_NodeID_busNumber 0x0000ffc0 67*4882a593Smuzhiyun #define OHCI1394_PhyControl 0x0EC 68*4882a593Smuzhiyun #define OHCI1394_PhyControl_Read(addr) (((addr) << 8) | 0x00008000) 69*4882a593Smuzhiyun #define OHCI1394_PhyControl_ReadDone 0x80000000 70*4882a593Smuzhiyun #define OHCI1394_PhyControl_ReadData(r) (((r) & 0x00ff0000) >> 16) 71*4882a593Smuzhiyun #define OHCI1394_PhyControl_Write(addr, data) (((addr) << 8) | (data) | 0x00004000) 72*4882a593Smuzhiyun #define OHCI1394_PhyControl_WritePending 0x00004000 73*4882a593Smuzhiyun #define OHCI1394_IsochronousCycleTimer 0x0F0 74*4882a593Smuzhiyun #define OHCI1394_AsReqFilterHiSet 0x100 75*4882a593Smuzhiyun #define OHCI1394_AsReqFilterHiClear 0x104 76*4882a593Smuzhiyun #define OHCI1394_AsReqFilterLoSet 0x108 77*4882a593Smuzhiyun #define OHCI1394_AsReqFilterLoClear 0x10C 78*4882a593Smuzhiyun #define OHCI1394_PhyReqFilterHiSet 0x110 79*4882a593Smuzhiyun #define OHCI1394_PhyReqFilterHiClear 0x114 80*4882a593Smuzhiyun #define OHCI1394_PhyReqFilterLoSet 0x118 81*4882a593Smuzhiyun #define OHCI1394_PhyReqFilterLoClear 0x11C 82*4882a593Smuzhiyun #define OHCI1394_PhyUpperBound 0x120 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #define OHCI1394_AsReqTrContextBase 0x180 85*4882a593Smuzhiyun #define OHCI1394_AsReqTrContextControlSet 0x180 86*4882a593Smuzhiyun #define OHCI1394_AsReqTrContextControlClear 0x184 87*4882a593Smuzhiyun #define OHCI1394_AsReqTrCommandPtr 0x18C 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #define OHCI1394_AsRspTrContextBase 0x1A0 90*4882a593Smuzhiyun #define OHCI1394_AsRspTrContextControlSet 0x1A0 91*4882a593Smuzhiyun #define OHCI1394_AsRspTrContextControlClear 0x1A4 92*4882a593Smuzhiyun #define OHCI1394_AsRspTrCommandPtr 0x1AC 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #define OHCI1394_AsReqRcvContextBase 0x1C0 95*4882a593Smuzhiyun #define OHCI1394_AsReqRcvContextControlSet 0x1C0 96*4882a593Smuzhiyun #define OHCI1394_AsReqRcvContextControlClear 0x1C4 97*4882a593Smuzhiyun #define OHCI1394_AsReqRcvCommandPtr 0x1CC 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun #define OHCI1394_AsRspRcvContextBase 0x1E0 100*4882a593Smuzhiyun #define OHCI1394_AsRspRcvContextControlSet 0x1E0 101*4882a593Smuzhiyun #define OHCI1394_AsRspRcvContextControlClear 0x1E4 102*4882a593Smuzhiyun #define OHCI1394_AsRspRcvCommandPtr 0x1EC 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* Isochronous transmit registers */ 105*4882a593Smuzhiyun #define OHCI1394_IsoXmitContextBase(n) (0x200 + 16 * (n)) 106*4882a593Smuzhiyun #define OHCI1394_IsoXmitContextControlSet(n) (0x200 + 16 * (n)) 107*4882a593Smuzhiyun #define OHCI1394_IsoXmitContextControlClear(n) (0x204 + 16 * (n)) 108*4882a593Smuzhiyun #define OHCI1394_IsoXmitCommandPtr(n) (0x20C + 16 * (n)) 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* Isochronous receive registers */ 111*4882a593Smuzhiyun #define OHCI1394_IsoRcvContextBase(n) (0x400 + 32 * (n)) 112*4882a593Smuzhiyun #define OHCI1394_IsoRcvContextControlSet(n) (0x400 + 32 * (n)) 113*4882a593Smuzhiyun #define OHCI1394_IsoRcvContextControlClear(n) (0x404 + 32 * (n)) 114*4882a593Smuzhiyun #define OHCI1394_IsoRcvCommandPtr(n) (0x40C + 32 * (n)) 115*4882a593Smuzhiyun #define OHCI1394_IsoRcvContextMatch(n) (0x410 + 32 * (n)) 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun /* Interrupts Mask/Events */ 118*4882a593Smuzhiyun #define OHCI1394_reqTxComplete 0x00000001 119*4882a593Smuzhiyun #define OHCI1394_respTxComplete 0x00000002 120*4882a593Smuzhiyun #define OHCI1394_ARRQ 0x00000004 121*4882a593Smuzhiyun #define OHCI1394_ARRS 0x00000008 122*4882a593Smuzhiyun #define OHCI1394_RQPkt 0x00000010 123*4882a593Smuzhiyun #define OHCI1394_RSPkt 0x00000020 124*4882a593Smuzhiyun #define OHCI1394_isochTx 0x00000040 125*4882a593Smuzhiyun #define OHCI1394_isochRx 0x00000080 126*4882a593Smuzhiyun #define OHCI1394_postedWriteErr 0x00000100 127*4882a593Smuzhiyun #define OHCI1394_lockRespErr 0x00000200 128*4882a593Smuzhiyun #define OHCI1394_selfIDComplete 0x00010000 129*4882a593Smuzhiyun #define OHCI1394_busReset 0x00020000 130*4882a593Smuzhiyun #define OHCI1394_regAccessFail 0x00040000 131*4882a593Smuzhiyun #define OHCI1394_phy 0x00080000 132*4882a593Smuzhiyun #define OHCI1394_cycleSynch 0x00100000 133*4882a593Smuzhiyun #define OHCI1394_cycle64Seconds 0x00200000 134*4882a593Smuzhiyun #define OHCI1394_cycleLost 0x00400000 135*4882a593Smuzhiyun #define OHCI1394_cycleInconsistent 0x00800000 136*4882a593Smuzhiyun #define OHCI1394_unrecoverableError 0x01000000 137*4882a593Smuzhiyun #define OHCI1394_cycleTooLong 0x02000000 138*4882a593Smuzhiyun #define OHCI1394_phyRegRcvd 0x04000000 139*4882a593Smuzhiyun #define OHCI1394_masterIntEnable 0x80000000 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #define OHCI1394_evt_no_status 0x0 142*4882a593Smuzhiyun #define OHCI1394_evt_long_packet 0x2 143*4882a593Smuzhiyun #define OHCI1394_evt_missing_ack 0x3 144*4882a593Smuzhiyun #define OHCI1394_evt_underrun 0x4 145*4882a593Smuzhiyun #define OHCI1394_evt_overrun 0x5 146*4882a593Smuzhiyun #define OHCI1394_evt_descriptor_read 0x6 147*4882a593Smuzhiyun #define OHCI1394_evt_data_read 0x7 148*4882a593Smuzhiyun #define OHCI1394_evt_data_write 0x8 149*4882a593Smuzhiyun #define OHCI1394_evt_bus_reset 0x9 150*4882a593Smuzhiyun #define OHCI1394_evt_timeout 0xa 151*4882a593Smuzhiyun #define OHCI1394_evt_tcode_err 0xb 152*4882a593Smuzhiyun #define OHCI1394_evt_reserved_b 0xc 153*4882a593Smuzhiyun #define OHCI1394_evt_reserved_c 0xd 154*4882a593Smuzhiyun #define OHCI1394_evt_unknown 0xe 155*4882a593Smuzhiyun #define OHCI1394_evt_flushed 0xf 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun #define OHCI1394_phy_tcode 0xe 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun #endif /* _FIREWIRE_OHCI_H */ 160