1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public
3*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive
4*4882a593Smuzhiyun * for more details.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2012 Cavium, Inc.
7*4882a593Smuzhiyun * Copyright (C) 2009 Wind River Systems,
8*4882a593Smuzhiyun * written by Ralf Baechle <ralf@linux-mips.org>
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/init.h>
12*4882a593Smuzhiyun #include <linux/slab.h>
13*4882a593Smuzhiyun #include <linux/io.h>
14*4882a593Smuzhiyun #include <linux/edac.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include <asm/octeon/cvmx.h>
17*4882a593Smuzhiyun #include <asm/octeon/cvmx-npi-defs.h>
18*4882a593Smuzhiyun #include <asm/octeon/cvmx-pci-defs.h>
19*4882a593Smuzhiyun #include <asm/octeon/octeon.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #include "edac_module.h"
22*4882a593Smuzhiyun
octeon_pci_poll(struct edac_pci_ctl_info * pci)23*4882a593Smuzhiyun static void octeon_pci_poll(struct edac_pci_ctl_info *pci)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun union cvmx_pci_cfg01 cfg01;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun cfg01.u32 = octeon_npi_read32(CVMX_NPI_PCI_CFG01);
28*4882a593Smuzhiyun if (cfg01.s.dpe) { /* Detected parity error */
29*4882a593Smuzhiyun edac_pci_handle_pe(pci, pci->ctl_name);
30*4882a593Smuzhiyun cfg01.s.dpe = 1; /* Reset */
31*4882a593Smuzhiyun octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun if (cfg01.s.sse) {
34*4882a593Smuzhiyun edac_pci_handle_npe(pci, "Signaled System Error");
35*4882a593Smuzhiyun cfg01.s.sse = 1; /* Reset */
36*4882a593Smuzhiyun octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun if (cfg01.s.rma) {
39*4882a593Smuzhiyun edac_pci_handle_npe(pci, "Received Master Abort");
40*4882a593Smuzhiyun cfg01.s.rma = 1; /* Reset */
41*4882a593Smuzhiyun octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun if (cfg01.s.rta) {
44*4882a593Smuzhiyun edac_pci_handle_npe(pci, "Received Target Abort");
45*4882a593Smuzhiyun cfg01.s.rta = 1; /* Reset */
46*4882a593Smuzhiyun octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun if (cfg01.s.sta) {
49*4882a593Smuzhiyun edac_pci_handle_npe(pci, "Signaled Target Abort");
50*4882a593Smuzhiyun cfg01.s.sta = 1; /* Reset */
51*4882a593Smuzhiyun octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun if (cfg01.s.mdpe) {
54*4882a593Smuzhiyun edac_pci_handle_npe(pci, "Master Data Parity Error");
55*4882a593Smuzhiyun cfg01.s.mdpe = 1; /* Reset */
56*4882a593Smuzhiyun octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
octeon_pci_probe(struct platform_device * pdev)60*4882a593Smuzhiyun static int octeon_pci_probe(struct platform_device *pdev)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun struct edac_pci_ctl_info *pci;
63*4882a593Smuzhiyun int res = 0;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun pci = edac_pci_alloc_ctl_info(0, "octeon_pci_err");
66*4882a593Smuzhiyun if (!pci)
67*4882a593Smuzhiyun return -ENOMEM;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun pci->dev = &pdev->dev;
70*4882a593Smuzhiyun platform_set_drvdata(pdev, pci);
71*4882a593Smuzhiyun pci->dev_name = dev_name(&pdev->dev);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun pci->mod_name = "octeon-pci";
74*4882a593Smuzhiyun pci->ctl_name = "octeon_pci_err";
75*4882a593Smuzhiyun pci->edac_check = octeon_pci_poll;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun if (edac_pci_add_device(pci, 0) > 0) {
78*4882a593Smuzhiyun pr_err("%s: edac_pci_add_device() failed\n", __func__);
79*4882a593Smuzhiyun goto err;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun return 0;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun err:
85*4882a593Smuzhiyun edac_pci_free_ctl_info(pci);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun return res;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
octeon_pci_remove(struct platform_device * pdev)90*4882a593Smuzhiyun static int octeon_pci_remove(struct platform_device *pdev)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun struct edac_pci_ctl_info *pci = platform_get_drvdata(pdev);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun edac_pci_del_device(&pdev->dev);
95*4882a593Smuzhiyun edac_pci_free_ctl_info(pci);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun return 0;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun static struct platform_driver octeon_pci_driver = {
101*4882a593Smuzhiyun .probe = octeon_pci_probe,
102*4882a593Smuzhiyun .remove = octeon_pci_remove,
103*4882a593Smuzhiyun .driver = {
104*4882a593Smuzhiyun .name = "octeon_pci_edac",
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun module_platform_driver(octeon_pci_driver);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun MODULE_LICENSE("GPL");
110*4882a593Smuzhiyun MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
111