1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * EDAC defs for Marvell MV64x60 bridge chip 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Author: Dave Jiang <djiang@mvista.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * 2007 (c) MontaVista Software, Inc. This file is licensed under 7*4882a593Smuzhiyun * the terms of the GNU General Public License version 2. This program 8*4882a593Smuzhiyun * is licensed "as is" without any warranty of any kind, whether express 9*4882a593Smuzhiyun * or implied. 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun #ifndef _MV64X60_EDAC_H_ 13*4882a593Smuzhiyun #define _MV64X60_EDAC_H_ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define MV64x60_REVISION " Ver: 2.0.0" 16*4882a593Smuzhiyun #define EDAC_MOD_STR "MV64x60_edac" 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define mv64x60_printk(level, fmt, arg...) \ 19*4882a593Smuzhiyun edac_printk(level, "MV64x60", fmt, ##arg) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define mv64x60_mc_printk(mci, level, fmt, arg...) \ 22*4882a593Smuzhiyun edac_mc_chipset_printk(mci, level, "MV64x60", fmt, ##arg) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* CPU Error Report Registers */ 25*4882a593Smuzhiyun #define MV64x60_CPU_ERR_ADDR_LO 0x00 /* 0x0070 */ 26*4882a593Smuzhiyun #define MV64x60_CPU_ERR_ADDR_HI 0x08 /* 0x0078 */ 27*4882a593Smuzhiyun #define MV64x60_CPU_ERR_DATA_LO 0x00 /* 0x0128 */ 28*4882a593Smuzhiyun #define MV64x60_CPU_ERR_DATA_HI 0x08 /* 0x0130 */ 29*4882a593Smuzhiyun #define MV64x60_CPU_ERR_PARITY 0x10 /* 0x0138 */ 30*4882a593Smuzhiyun #define MV64x60_CPU_ERR_CAUSE 0x18 /* 0x0140 */ 31*4882a593Smuzhiyun #define MV64x60_CPU_ERR_MASK 0x20 /* 0x0148 */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define MV64x60_CPU_CAUSE_MASK 0x07ffffff 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* SRAM Error Report Registers */ 36*4882a593Smuzhiyun #define MV64X60_SRAM_ERR_CAUSE 0x08 /* 0x0388 */ 37*4882a593Smuzhiyun #define MV64X60_SRAM_ERR_ADDR_LO 0x10 /* 0x0390 */ 38*4882a593Smuzhiyun #define MV64X60_SRAM_ERR_ADDR_HI 0x78 /* 0x03f8 */ 39*4882a593Smuzhiyun #define MV64X60_SRAM_ERR_DATA_LO 0x18 /* 0x0398 */ 40*4882a593Smuzhiyun #define MV64X60_SRAM_ERR_DATA_HI 0x20 /* 0x03a0 */ 41*4882a593Smuzhiyun #define MV64X60_SRAM_ERR_PARITY 0x28 /* 0x03a8 */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* SDRAM Controller Registers */ 44*4882a593Smuzhiyun #define MV64X60_SDRAM_CONFIG 0x00 /* 0x1400 */ 45*4882a593Smuzhiyun #define MV64X60_SDRAM_ERR_DATA_HI 0x40 /* 0x1440 */ 46*4882a593Smuzhiyun #define MV64X60_SDRAM_ERR_DATA_LO 0x44 /* 0x1444 */ 47*4882a593Smuzhiyun #define MV64X60_SDRAM_ERR_ECC_RCVD 0x48 /* 0x1448 */ 48*4882a593Smuzhiyun #define MV64X60_SDRAM_ERR_ECC_CALC 0x4c /* 0x144c */ 49*4882a593Smuzhiyun #define MV64X60_SDRAM_ERR_ADDR 0x50 /* 0x1450 */ 50*4882a593Smuzhiyun #define MV64X60_SDRAM_ERR_ECC_CNTL 0x54 /* 0x1454 */ 51*4882a593Smuzhiyun #define MV64X60_SDRAM_ERR_ECC_ERR_CNT 0x58 /* 0x1458 */ 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define MV64X60_SDRAM_REGISTERED 0x20000 54*4882a593Smuzhiyun #define MV64X60_SDRAM_ECC 0x40000 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #ifdef CONFIG_PCI 57*4882a593Smuzhiyun /* 58*4882a593Smuzhiyun * Bit 0 of MV64x60_PCIx_ERR_MASK does not exist on the 64360 and because of 59*4882a593Smuzhiyun * errata FEr-#11 and FEr-##16 for the 64460, it should be 0 on that chip as 60*4882a593Smuzhiyun * well. IOW, don't set bit 0. 61*4882a593Smuzhiyun */ 62*4882a593Smuzhiyun #define MV64X60_PCIx_ERR_MASK_VAL 0x00a50c24 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* Register offsets from PCIx error address low register */ 65*4882a593Smuzhiyun #define MV64X60_PCI_ERROR_ADDR_LO 0x00 66*4882a593Smuzhiyun #define MV64X60_PCI_ERROR_ADDR_HI 0x04 67*4882a593Smuzhiyun #define MV64X60_PCI_ERROR_ATTR 0x08 68*4882a593Smuzhiyun #define MV64X60_PCI_ERROR_CMD 0x10 69*4882a593Smuzhiyun #define MV64X60_PCI_ERROR_CAUSE 0x18 70*4882a593Smuzhiyun #define MV64X60_PCI_ERROR_MASK 0x1c 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define MV64X60_PCI_ERR_SWrPerr 0x0002 73*4882a593Smuzhiyun #define MV64X60_PCI_ERR_SRdPerr 0x0004 74*4882a593Smuzhiyun #define MV64X60_PCI_ERR_MWrPerr 0x0020 75*4882a593Smuzhiyun #define MV64X60_PCI_ERR_MRdPerr 0x0040 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define MV64X60_PCI_PE_MASK (MV64X60_PCI_ERR_SWrPerr | \ 78*4882a593Smuzhiyun MV64X60_PCI_ERR_SRdPerr | \ 79*4882a593Smuzhiyun MV64X60_PCI_ERR_MWrPerr | \ 80*4882a593Smuzhiyun MV64X60_PCI_ERR_MRdPerr) 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun struct mv64x60_pci_pdata { 83*4882a593Smuzhiyun int pci_hose; 84*4882a593Smuzhiyun void __iomem *pci_vbase; 85*4882a593Smuzhiyun char *name; 86*4882a593Smuzhiyun int irq; 87*4882a593Smuzhiyun int edac_idx; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #endif /* CONFIG_PCI */ 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun struct mv64x60_mc_pdata { 93*4882a593Smuzhiyun void __iomem *mc_vbase; 94*4882a593Smuzhiyun int total_mem; 95*4882a593Smuzhiyun char *name; 96*4882a593Smuzhiyun int irq; 97*4882a593Smuzhiyun int edac_idx; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun struct mv64x60_cpu_pdata { 101*4882a593Smuzhiyun void __iomem *cpu_vbase[2]; 102*4882a593Smuzhiyun char *name; 103*4882a593Smuzhiyun int irq; 104*4882a593Smuzhiyun int edac_idx; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun struct mv64x60_sram_pdata { 108*4882a593Smuzhiyun void __iomem *sram_vbase; 109*4882a593Smuzhiyun char *name; 110*4882a593Smuzhiyun int irq; 111*4882a593Smuzhiyun int edac_idx; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun #endif 115