1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Freescale MPC85xx Memory Controller kernel module 3*4882a593Smuzhiyun * Author: Dave Jiang <djiang@mvista.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under 6*4882a593Smuzhiyun * the terms of the GNU General Public License version 2. This program 7*4882a593Smuzhiyun * is licensed "as is" without any warranty of any kind, whether express 8*4882a593Smuzhiyun * or implied. 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun #ifndef _MPC85XX_EDAC_H_ 12*4882a593Smuzhiyun #define _MPC85XX_EDAC_H_ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define MPC85XX_REVISION " Ver: 2.0.0" 15*4882a593Smuzhiyun #define EDAC_MOD_STR "MPC85xx_edac" 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define mpc85xx_printk(level, fmt, arg...) \ 18*4882a593Smuzhiyun edac_printk(level, "MPC85xx", fmt, ##arg) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* 21*4882a593Smuzhiyun * L2 Err defines 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun #define MPC85XX_L2_ERRINJHI 0x0000 24*4882a593Smuzhiyun #define MPC85XX_L2_ERRINJLO 0x0004 25*4882a593Smuzhiyun #define MPC85XX_L2_ERRINJCTL 0x0008 26*4882a593Smuzhiyun #define MPC85XX_L2_CAPTDATAHI 0x0020 27*4882a593Smuzhiyun #define MPC85XX_L2_CAPTDATALO 0x0024 28*4882a593Smuzhiyun #define MPC85XX_L2_CAPTECC 0x0028 29*4882a593Smuzhiyun #define MPC85XX_L2_ERRDET 0x0040 30*4882a593Smuzhiyun #define MPC85XX_L2_ERRDIS 0x0044 31*4882a593Smuzhiyun #define MPC85XX_L2_ERRINTEN 0x0048 32*4882a593Smuzhiyun #define MPC85XX_L2_ERRATTR 0x004c 33*4882a593Smuzhiyun #define MPC85XX_L2_ERRADDR 0x0050 34*4882a593Smuzhiyun #define MPC85XX_L2_ERRCTL 0x0058 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* Error Interrupt Enable */ 37*4882a593Smuzhiyun #define L2_EIE_L2CFGINTEN 0x1 38*4882a593Smuzhiyun #define L2_EIE_SBECCINTEN 0x4 39*4882a593Smuzhiyun #define L2_EIE_MBECCINTEN 0x8 40*4882a593Smuzhiyun #define L2_EIE_TPARINTEN 0x10 41*4882a593Smuzhiyun #define L2_EIE_MASK (L2_EIE_L2CFGINTEN | L2_EIE_SBECCINTEN | \ 42*4882a593Smuzhiyun L2_EIE_MBECCINTEN | L2_EIE_TPARINTEN) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* Error Detect */ 45*4882a593Smuzhiyun #define L2_EDE_L2CFGERR 0x1 46*4882a593Smuzhiyun #define L2_EDE_SBECCERR 0x4 47*4882a593Smuzhiyun #define L2_EDE_MBECCERR 0x8 48*4882a593Smuzhiyun #define L2_EDE_TPARERR 0x10 49*4882a593Smuzhiyun #define L2_EDE_MULL2ERR 0x80000000 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define L2_EDE_CE_MASK L2_EDE_SBECCERR 52*4882a593Smuzhiyun #define L2_EDE_UE_MASK (L2_EDE_L2CFGERR | L2_EDE_MBECCERR | \ 53*4882a593Smuzhiyun L2_EDE_TPARERR) 54*4882a593Smuzhiyun #define L2_EDE_MASK (L2_EDE_L2CFGERR | L2_EDE_SBECCERR | \ 55*4882a593Smuzhiyun L2_EDE_MBECCERR | L2_EDE_TPARERR | L2_EDE_MULL2ERR) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* 58*4882a593Smuzhiyun * PCI Err defines 59*4882a593Smuzhiyun */ 60*4882a593Smuzhiyun #define PCI_EDE_TOE 0x00000001 61*4882a593Smuzhiyun #define PCI_EDE_SCM 0x00000002 62*4882a593Smuzhiyun #define PCI_EDE_IRMSV 0x00000004 63*4882a593Smuzhiyun #define PCI_EDE_ORMSV 0x00000008 64*4882a593Smuzhiyun #define PCI_EDE_OWMSV 0x00000010 65*4882a593Smuzhiyun #define PCI_EDE_TGT_ABRT 0x00000020 66*4882a593Smuzhiyun #define PCI_EDE_MST_ABRT 0x00000040 67*4882a593Smuzhiyun #define PCI_EDE_TGT_PERR 0x00000080 68*4882a593Smuzhiyun #define PCI_EDE_MST_PERR 0x00000100 69*4882a593Smuzhiyun #define PCI_EDE_RCVD_SERR 0x00000200 70*4882a593Smuzhiyun #define PCI_EDE_ADDR_PERR 0x00000400 71*4882a593Smuzhiyun #define PCI_EDE_MULTI_ERR 0x80000000 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define PCI_EDE_PERR_MASK (PCI_EDE_TGT_PERR | PCI_EDE_MST_PERR | \ 74*4882a593Smuzhiyun PCI_EDE_ADDR_PERR) 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define MPC85XX_PCI_ERR_DR 0x0000 77*4882a593Smuzhiyun #define MPC85XX_PCI_ERR_CAP_DR 0x0004 78*4882a593Smuzhiyun #define MPC85XX_PCI_ERR_EN 0x0008 79*4882a593Smuzhiyun #define PEX_ERR_ICCAIE_EN_BIT 0x00020000 80*4882a593Smuzhiyun #define MPC85XX_PCI_ERR_ATTRIB 0x000c 81*4882a593Smuzhiyun #define MPC85XX_PCI_ERR_ADDR 0x0010 82*4882a593Smuzhiyun #define PEX_ERR_ICCAD_DISR_BIT 0x00020000 83*4882a593Smuzhiyun #define MPC85XX_PCI_ERR_EXT_ADDR 0x0014 84*4882a593Smuzhiyun #define MPC85XX_PCI_ERR_DL 0x0018 85*4882a593Smuzhiyun #define MPC85XX_PCI_ERR_DH 0x001c 86*4882a593Smuzhiyun #define MPC85XX_PCI_GAS_TIMR 0x0020 87*4882a593Smuzhiyun #define MPC85XX_PCI_PCIX_TIMR 0x0024 88*4882a593Smuzhiyun #define MPC85XX_PCIE_ERR_CAP_R0 0x0028 89*4882a593Smuzhiyun #define MPC85XX_PCIE_ERR_CAP_R1 0x002c 90*4882a593Smuzhiyun #define MPC85XX_PCIE_ERR_CAP_R2 0x0030 91*4882a593Smuzhiyun #define MPC85XX_PCIE_ERR_CAP_R3 0x0034 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun struct mpc85xx_l2_pdata { 94*4882a593Smuzhiyun char *name; 95*4882a593Smuzhiyun int edac_idx; 96*4882a593Smuzhiyun void __iomem *l2_vbase; 97*4882a593Smuzhiyun int irq; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun struct mpc85xx_pci_pdata { 101*4882a593Smuzhiyun char *name; 102*4882a593Smuzhiyun bool is_pcie; 103*4882a593Smuzhiyun int edac_idx; 104*4882a593Smuzhiyun void __iomem *pci_vbase; 105*4882a593Smuzhiyun int irq; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #endif 109