1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _EDAC_MCE_AMD_H 3*4882a593Smuzhiyun #define _EDAC_MCE_AMD_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <linux/notifier.h> 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <asm/mce.h> 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define EC(x) ((x) & 0xffff) 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define LOW_SYNDROME(x) (((x) >> 15) & 0xff) 12*4882a593Smuzhiyun #define HIGH_SYNDROME(x) (((x) >> 24) & 0xff) 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define TLB_ERROR(x) (((x) & 0xFFF0) == 0x0010) 15*4882a593Smuzhiyun #define MEM_ERROR(x) (((x) & 0xFF00) == 0x0100) 16*4882a593Smuzhiyun #define BUS_ERROR(x) (((x) & 0xF800) == 0x0800) 17*4882a593Smuzhiyun #define INT_ERROR(x) (((x) & 0xF4FF) == 0x0400) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define TT(x) (((x) >> 2) & 0x3) 20*4882a593Smuzhiyun #define TT_MSG(x) tt_msgs[TT(x)] 21*4882a593Smuzhiyun #define II(x) (((x) >> 2) & 0x3) 22*4882a593Smuzhiyun #define II_MSG(x) ii_msgs[II(x)] 23*4882a593Smuzhiyun #define LL(x) ((x) & 0x3) 24*4882a593Smuzhiyun #define LL_MSG(x) ll_msgs[LL(x)] 25*4882a593Smuzhiyun #define TO(x) (((x) >> 8) & 0x1) 26*4882a593Smuzhiyun #define TO_MSG(x) to_msgs[TO(x)] 27*4882a593Smuzhiyun #define PP(x) (((x) >> 9) & 0x3) 28*4882a593Smuzhiyun #define PP_MSG(x) pp_msgs[PP(x)] 29*4882a593Smuzhiyun #define UU(x) (((x) >> 8) & 0x3) 30*4882a593Smuzhiyun #define UU_MSG(x) uu_msgs[UU(x)] 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define R4(x) (((x) >> 4) & 0xf) 33*4882a593Smuzhiyun #define R4_MSG(x) ((R4(x) < 9) ? rrrr_msgs[R4(x)] : "Wrong R4!") 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun extern const char * const pp_msgs[]; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun enum tt_ids { 38*4882a593Smuzhiyun TT_INSTR = 0, 39*4882a593Smuzhiyun TT_DATA, 40*4882a593Smuzhiyun TT_GEN, 41*4882a593Smuzhiyun TT_RESV, 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun enum ll_ids { 45*4882a593Smuzhiyun LL_RESV = 0, 46*4882a593Smuzhiyun LL_L1, 47*4882a593Smuzhiyun LL_L2, 48*4882a593Smuzhiyun LL_LG, 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun enum ii_ids { 52*4882a593Smuzhiyun II_MEM = 0, 53*4882a593Smuzhiyun II_RESV, 54*4882a593Smuzhiyun II_IO, 55*4882a593Smuzhiyun II_GEN, 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun enum rrrr_ids { 59*4882a593Smuzhiyun R4_GEN = 0, 60*4882a593Smuzhiyun R4_RD, 61*4882a593Smuzhiyun R4_WR, 62*4882a593Smuzhiyun R4_DRD, 63*4882a593Smuzhiyun R4_DWR, 64*4882a593Smuzhiyun R4_IRD, 65*4882a593Smuzhiyun R4_PREF, 66*4882a593Smuzhiyun R4_EVICT, 67*4882a593Smuzhiyun R4_SNOOP, 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* 71*4882a593Smuzhiyun * per-family decoder ops 72*4882a593Smuzhiyun */ 73*4882a593Smuzhiyun struct amd_decoder_ops { 74*4882a593Smuzhiyun bool (*mc0_mce)(u16, u8); 75*4882a593Smuzhiyun bool (*mc1_mce)(u16, u8); 76*4882a593Smuzhiyun bool (*mc2_mce)(u16, u8); 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun void amd_register_ecc_decoder(void (*f)(int, struct mce *)); 80*4882a593Smuzhiyun void amd_unregister_ecc_decoder(void (*f)(int, struct mce *)); 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #endif /* _EDAC_MCE_AMD_H */ 83