1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Freescale Memory Controller kernel module
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Author: York Sun <york.sun@nxp.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright 2016 NXP Semiconductor
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Derived from mpc85xx_edac.c
9*4882a593Smuzhiyun * Author: Dave Jiang <djiang@mvista.com>
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
12*4882a593Smuzhiyun * the terms of the GNU General Public License version 2. This program
13*4882a593Smuzhiyun * is licensed "as is" without any warranty of any kind, whether express
14*4882a593Smuzhiyun * or implied.
15*4882a593Smuzhiyun */
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include "edac_module.h"
20*4882a593Smuzhiyun #include "fsl_ddr_edac.h"
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun static const struct of_device_id fsl_ddr_mc_err_of_match[] = {
23*4882a593Smuzhiyun { .compatible = "fsl,qoriq-memory-controller", },
24*4882a593Smuzhiyun {},
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, fsl_ddr_mc_err_of_match);
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun static struct platform_driver fsl_ddr_mc_err_driver = {
29*4882a593Smuzhiyun .probe = fsl_mc_err_probe,
30*4882a593Smuzhiyun .remove = fsl_mc_err_remove,
31*4882a593Smuzhiyun .driver = {
32*4882a593Smuzhiyun .name = "fsl_ddr_mc_err",
33*4882a593Smuzhiyun .of_match_table = fsl_ddr_mc_err_of_match,
34*4882a593Smuzhiyun },
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun
fsl_ddr_mc_init(void)37*4882a593Smuzhiyun static int __init fsl_ddr_mc_init(void)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun int res;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /* make sure error reporting method is sane */
42*4882a593Smuzhiyun switch (edac_op_state) {
43*4882a593Smuzhiyun case EDAC_OPSTATE_POLL:
44*4882a593Smuzhiyun case EDAC_OPSTATE_INT:
45*4882a593Smuzhiyun break;
46*4882a593Smuzhiyun default:
47*4882a593Smuzhiyun edac_op_state = EDAC_OPSTATE_INT;
48*4882a593Smuzhiyun break;
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun res = platform_driver_register(&fsl_ddr_mc_err_driver);
52*4882a593Smuzhiyun if (res) {
53*4882a593Smuzhiyun pr_err("MC fails to register\n");
54*4882a593Smuzhiyun return res;
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun return 0;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun module_init(fsl_ddr_mc_init);
61*4882a593Smuzhiyun
fsl_ddr_mc_exit(void)62*4882a593Smuzhiyun static void __exit fsl_ddr_mc_exit(void)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun platform_driver_unregister(&fsl_ddr_mc_err_driver);
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun module_exit(fsl_ddr_mc_exit);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun MODULE_LICENSE("GPL");
70*4882a593Smuzhiyun MODULE_AUTHOR("NXP Semiconductor");
71*4882a593Smuzhiyun module_param(edac_op_state, int, 0444);
72*4882a593Smuzhiyun MODULE_PARM_DESC(edac_op_state,
73*4882a593Smuzhiyun "EDAC Error Reporting state: 0=Poll, 2=Interrupt");
74