1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2011-2012 Calxeda, Inc.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun #include <linux/types.h>
6*4882a593Smuzhiyun #include <linux/kernel.h>
7*4882a593Smuzhiyun #include <linux/ctype.h>
8*4882a593Smuzhiyun #include <linux/edac.h>
9*4882a593Smuzhiyun #include <linux/interrupt.h>
10*4882a593Smuzhiyun #include <linux/platform_device.h>
11*4882a593Smuzhiyun #include <linux/of_platform.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include "edac_module.h"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define SR_CLR_SB_ECC_INTR 0x0
16*4882a593Smuzhiyun #define SR_CLR_DB_ECC_INTR 0x4
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun struct hb_l2_drvdata {
19*4882a593Smuzhiyun void __iomem *base;
20*4882a593Smuzhiyun int sb_irq;
21*4882a593Smuzhiyun int db_irq;
22*4882a593Smuzhiyun };
23*4882a593Smuzhiyun
highbank_l2_err_handler(int irq,void * dev_id)24*4882a593Smuzhiyun static irqreturn_t highbank_l2_err_handler(int irq, void *dev_id)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun struct edac_device_ctl_info *dci = dev_id;
27*4882a593Smuzhiyun struct hb_l2_drvdata *drvdata = dci->pvt_info;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun if (irq == drvdata->sb_irq) {
30*4882a593Smuzhiyun writel(1, drvdata->base + SR_CLR_SB_ECC_INTR);
31*4882a593Smuzhiyun edac_device_handle_ce(dci, 0, 0, dci->ctl_name);
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun if (irq == drvdata->db_irq) {
34*4882a593Smuzhiyun writel(1, drvdata->base + SR_CLR_DB_ECC_INTR);
35*4882a593Smuzhiyun edac_device_handle_ue(dci, 0, 0, dci->ctl_name);
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun return IRQ_HANDLED;
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun static const struct of_device_id hb_l2_err_of_match[] = {
42*4882a593Smuzhiyun { .compatible = "calxeda,hb-sregs-l2-ecc", },
43*4882a593Smuzhiyun {},
44*4882a593Smuzhiyun };
45*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, hb_l2_err_of_match);
46*4882a593Smuzhiyun
highbank_l2_err_probe(struct platform_device * pdev)47*4882a593Smuzhiyun static int highbank_l2_err_probe(struct platform_device *pdev)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun const struct of_device_id *id;
50*4882a593Smuzhiyun struct edac_device_ctl_info *dci;
51*4882a593Smuzhiyun struct hb_l2_drvdata *drvdata;
52*4882a593Smuzhiyun struct resource *r;
53*4882a593Smuzhiyun int res = 0;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun dci = edac_device_alloc_ctl_info(sizeof(*drvdata), "cpu",
56*4882a593Smuzhiyun 1, "L", 1, 2, NULL, 0, 0);
57*4882a593Smuzhiyun if (!dci)
58*4882a593Smuzhiyun return -ENOMEM;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun drvdata = dci->pvt_info;
61*4882a593Smuzhiyun dci->dev = &pdev->dev;
62*4882a593Smuzhiyun platform_set_drvdata(pdev, dci);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
65*4882a593Smuzhiyun return -ENOMEM;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
68*4882a593Smuzhiyun if (!r) {
69*4882a593Smuzhiyun dev_err(&pdev->dev, "Unable to get mem resource\n");
70*4882a593Smuzhiyun res = -ENODEV;
71*4882a593Smuzhiyun goto err;
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun if (!devm_request_mem_region(&pdev->dev, r->start,
75*4882a593Smuzhiyun resource_size(r), dev_name(&pdev->dev))) {
76*4882a593Smuzhiyun dev_err(&pdev->dev, "Error while requesting mem region\n");
77*4882a593Smuzhiyun res = -EBUSY;
78*4882a593Smuzhiyun goto err;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
82*4882a593Smuzhiyun if (!drvdata->base) {
83*4882a593Smuzhiyun dev_err(&pdev->dev, "Unable to map regs\n");
84*4882a593Smuzhiyun res = -ENOMEM;
85*4882a593Smuzhiyun goto err;
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun id = of_match_device(hb_l2_err_of_match, &pdev->dev);
89*4882a593Smuzhiyun dci->mod_name = pdev->dev.driver->name;
90*4882a593Smuzhiyun dci->ctl_name = id ? id->compatible : "unknown";
91*4882a593Smuzhiyun dci->dev_name = dev_name(&pdev->dev);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun if (edac_device_add_device(dci))
94*4882a593Smuzhiyun goto err;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun drvdata->db_irq = platform_get_irq(pdev, 0);
97*4882a593Smuzhiyun res = devm_request_irq(&pdev->dev, drvdata->db_irq,
98*4882a593Smuzhiyun highbank_l2_err_handler,
99*4882a593Smuzhiyun 0, dev_name(&pdev->dev), dci);
100*4882a593Smuzhiyun if (res < 0)
101*4882a593Smuzhiyun goto err2;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun drvdata->sb_irq = platform_get_irq(pdev, 1);
104*4882a593Smuzhiyun res = devm_request_irq(&pdev->dev, drvdata->sb_irq,
105*4882a593Smuzhiyun highbank_l2_err_handler,
106*4882a593Smuzhiyun 0, dev_name(&pdev->dev), dci);
107*4882a593Smuzhiyun if (res < 0)
108*4882a593Smuzhiyun goto err2;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun devres_close_group(&pdev->dev, NULL);
111*4882a593Smuzhiyun return 0;
112*4882a593Smuzhiyun err2:
113*4882a593Smuzhiyun edac_device_del_device(&pdev->dev);
114*4882a593Smuzhiyun err:
115*4882a593Smuzhiyun devres_release_group(&pdev->dev, NULL);
116*4882a593Smuzhiyun edac_device_free_ctl_info(dci);
117*4882a593Smuzhiyun return res;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun
highbank_l2_err_remove(struct platform_device * pdev)120*4882a593Smuzhiyun static int highbank_l2_err_remove(struct platform_device *pdev)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun struct edac_device_ctl_info *dci = platform_get_drvdata(pdev);
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun edac_device_del_device(&pdev->dev);
125*4882a593Smuzhiyun edac_device_free_ctl_info(dci);
126*4882a593Smuzhiyun return 0;
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun static struct platform_driver highbank_l2_edac_driver = {
130*4882a593Smuzhiyun .probe = highbank_l2_err_probe,
131*4882a593Smuzhiyun .remove = highbank_l2_err_remove,
132*4882a593Smuzhiyun .driver = {
133*4882a593Smuzhiyun .name = "hb_l2_edac",
134*4882a593Smuzhiyun .of_match_table = hb_l2_err_of_match,
135*4882a593Smuzhiyun },
136*4882a593Smuzhiyun };
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun module_platform_driver(highbank_l2_edac_driver);
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
141*4882a593Smuzhiyun MODULE_AUTHOR("Calxeda, Inc.");
142*4882a593Smuzhiyun MODULE_DESCRIPTION("EDAC Driver for Calxeda Highbank L2 Cache");
143