1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Freescale Memory Controller kernel module 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Support Power-based SoCs including MPC85xx, MPC86xx, MPC83xx and 5*4882a593Smuzhiyun * ARM-based Layerscape SoCs including LS2xxx and LS1021A. Originally 6*4882a593Smuzhiyun * split out from mpc85xx_edac EDAC driver. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Author: Dave Jiang <djiang@mvista.com> 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under 11*4882a593Smuzhiyun * the terms of the GNU General Public License version 2. This program 12*4882a593Smuzhiyun * is licensed "as is" without any warranty of any kind, whether express 13*4882a593Smuzhiyun * or implied. 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun #ifndef _FSL_DDR_EDAC_H_ 17*4882a593Smuzhiyun #define _FSL_DDR_EDAC_H_ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define fsl_mc_printk(mci, level, fmt, arg...) \ 20*4882a593Smuzhiyun edac_mc_chipset_printk(mci, level, "FSL_DDR", fmt, ##arg) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* 23*4882a593Smuzhiyun * DRAM error defines 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* DDR_SDRAM_CFG */ 27*4882a593Smuzhiyun #define FSL_MC_DDR_SDRAM_CFG 0x0110 28*4882a593Smuzhiyun #define FSL_MC_CS_BNDS_0 0x0000 29*4882a593Smuzhiyun #define FSL_MC_CS_BNDS_OFS 0x0008 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define FSL_MC_DATA_ERR_INJECT_HI 0x0e00 32*4882a593Smuzhiyun #define FSL_MC_DATA_ERR_INJECT_LO 0x0e04 33*4882a593Smuzhiyun #define FSL_MC_ECC_ERR_INJECT 0x0e08 34*4882a593Smuzhiyun #define FSL_MC_CAPTURE_DATA_HI 0x0e20 35*4882a593Smuzhiyun #define FSL_MC_CAPTURE_DATA_LO 0x0e24 36*4882a593Smuzhiyun #define FSL_MC_CAPTURE_ECC 0x0e28 37*4882a593Smuzhiyun #define FSL_MC_ERR_DETECT 0x0e40 38*4882a593Smuzhiyun #define FSL_MC_ERR_DISABLE 0x0e44 39*4882a593Smuzhiyun #define FSL_MC_ERR_INT_EN 0x0e48 40*4882a593Smuzhiyun #define FSL_MC_CAPTURE_ATRIBUTES 0x0e4c 41*4882a593Smuzhiyun #define FSL_MC_CAPTURE_ADDRESS 0x0e50 42*4882a593Smuzhiyun #define FSL_MC_CAPTURE_EXT_ADDRESS 0x0e54 43*4882a593Smuzhiyun #define FSL_MC_ERR_SBE 0x0e58 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define DSC_MEM_EN 0x80000000 46*4882a593Smuzhiyun #define DSC_ECC_EN 0x20000000 47*4882a593Smuzhiyun #define DSC_RD_EN 0x10000000 48*4882a593Smuzhiyun #define DSC_DBW_MASK 0x00180000 49*4882a593Smuzhiyun #define DSC_DBW_32 0x00080000 50*4882a593Smuzhiyun #define DSC_DBW_64 0x00000000 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define DSC_SDTYPE_MASK 0x07000000 53*4882a593Smuzhiyun #define DSC_X32_EN 0x00000020 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* Err_Int_En */ 56*4882a593Smuzhiyun #define DDR_EIE_MSEE 0x1 /* memory select */ 57*4882a593Smuzhiyun #define DDR_EIE_SBEE 0x4 /* single-bit ECC error */ 58*4882a593Smuzhiyun #define DDR_EIE_MBEE 0x8 /* multi-bit ECC error */ 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* Err_Detect */ 61*4882a593Smuzhiyun #define DDR_EDE_MSE 0x1 /* memory select */ 62*4882a593Smuzhiyun #define DDR_EDE_SBE 0x4 /* single-bit ECC error */ 63*4882a593Smuzhiyun #define DDR_EDE_MBE 0x8 /* multi-bit ECC error */ 64*4882a593Smuzhiyun #define DDR_EDE_MME 0x80000000 /* multiple memory errors */ 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* Err_Disable */ 67*4882a593Smuzhiyun #define DDR_EDI_MSED 0x1 /* memory select disable */ 68*4882a593Smuzhiyun #define DDR_EDI_SBED 0x4 /* single-bit ECC error disable */ 69*4882a593Smuzhiyun #define DDR_EDI_MBED 0x8 /* multi-bit ECC error disable */ 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun struct fsl_mc_pdata { 72*4882a593Smuzhiyun char *name; 73*4882a593Smuzhiyun int edac_idx; 74*4882a593Smuzhiyun void __iomem *mc_vbase; 75*4882a593Smuzhiyun int irq; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun int fsl_mc_err_probe(struct platform_device *op); 78*4882a593Smuzhiyun int fsl_mc_err_remove(struct platform_device *op); 79*4882a593Smuzhiyun #endif 80