1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * amd8111_edac.h, EDAC defs for AMD8111 hypertransport chip 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2008 Wind River Systems, Inc. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Authors: Cao Qingtao <qingtao.cao@windriver.com> 8*4882a593Smuzhiyun * Benjamin Walsh <benjamin.walsh@windriver.com> 9*4882a593Smuzhiyun * Hu Yongqi <yongqi.hu@windriver.com> 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef _AMD8111_EDAC_H_ 13*4882a593Smuzhiyun #define _AMD8111_EDAC_H_ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /************************************************************ 16*4882a593Smuzhiyun * PCI Bridge Status and Command Register, DevA:0x04 17*4882a593Smuzhiyun ************************************************************/ 18*4882a593Smuzhiyun #define REG_PCI_STSCMD 0x04 19*4882a593Smuzhiyun enum pci_stscmd_bits { 20*4882a593Smuzhiyun PCI_STSCMD_SSE = BIT(30), 21*4882a593Smuzhiyun PCI_STSCMD_RMA = BIT(29), 22*4882a593Smuzhiyun PCI_STSCMD_RTA = BIT(28), 23*4882a593Smuzhiyun PCI_STSCMD_SERREN = BIT(8), 24*4882a593Smuzhiyun PCI_STSCMD_CLEAR_MASK = (PCI_STSCMD_SSE | 25*4882a593Smuzhiyun PCI_STSCMD_RMA | 26*4882a593Smuzhiyun PCI_STSCMD_RTA) 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /************************************************************ 30*4882a593Smuzhiyun * PCI Bridge Memory Base-Limit Register, DevA:0x1c 31*4882a593Smuzhiyun ************************************************************/ 32*4882a593Smuzhiyun #define REG_MEM_LIM 0x1c 33*4882a593Smuzhiyun enum mem_limit_bits { 34*4882a593Smuzhiyun MEM_LIMIT_DPE = BIT(31), 35*4882a593Smuzhiyun MEM_LIMIT_RSE = BIT(30), 36*4882a593Smuzhiyun MEM_LIMIT_RMA = BIT(29), 37*4882a593Smuzhiyun MEM_LIMIT_RTA = BIT(28), 38*4882a593Smuzhiyun MEM_LIMIT_STA = BIT(27), 39*4882a593Smuzhiyun MEM_LIMIT_MDPE = BIT(24), 40*4882a593Smuzhiyun MEM_LIMIT_CLEAR_MASK = (MEM_LIMIT_DPE | 41*4882a593Smuzhiyun MEM_LIMIT_RSE | 42*4882a593Smuzhiyun MEM_LIMIT_RMA | 43*4882a593Smuzhiyun MEM_LIMIT_RTA | 44*4882a593Smuzhiyun MEM_LIMIT_STA | 45*4882a593Smuzhiyun MEM_LIMIT_MDPE) 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /************************************************************ 49*4882a593Smuzhiyun * HyperTransport Link Control Register, DevA:0xc4 50*4882a593Smuzhiyun ************************************************************/ 51*4882a593Smuzhiyun #define REG_HT_LINK 0xc4 52*4882a593Smuzhiyun enum ht_link_bits { 53*4882a593Smuzhiyun HT_LINK_LKFAIL = BIT(4), 54*4882a593Smuzhiyun HT_LINK_CRCFEN = BIT(1), 55*4882a593Smuzhiyun HT_LINK_CLEAR_MASK = (HT_LINK_LKFAIL) 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /************************************************************ 59*4882a593Smuzhiyun * PCI Bridge Interrupt and Bridge Control, DevA:0x3c 60*4882a593Smuzhiyun ************************************************************/ 61*4882a593Smuzhiyun #define REG_PCI_INTBRG_CTRL 0x3c 62*4882a593Smuzhiyun enum pci_intbrg_ctrl_bits { 63*4882a593Smuzhiyun PCI_INTBRG_CTRL_DTSERREN = BIT(27), 64*4882a593Smuzhiyun PCI_INTBRG_CTRL_DTSTAT = BIT(26), 65*4882a593Smuzhiyun PCI_INTBRG_CTRL_MARSP = BIT(21), 66*4882a593Smuzhiyun PCI_INTBRG_CTRL_SERREN = BIT(17), 67*4882a593Smuzhiyun PCI_INTBRG_CTRL_PEREN = BIT(16), 68*4882a593Smuzhiyun PCI_INTBRG_CTRL_CLEAR_MASK = (PCI_INTBRG_CTRL_DTSTAT), 69*4882a593Smuzhiyun PCI_INTBRG_CTRL_POLL_MASK = (PCI_INTBRG_CTRL_DTSERREN | 70*4882a593Smuzhiyun PCI_INTBRG_CTRL_MARSP | 71*4882a593Smuzhiyun PCI_INTBRG_CTRL_SERREN) 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /************************************************************ 75*4882a593Smuzhiyun * I/O Control 1 Register, DevB:0x40 76*4882a593Smuzhiyun ************************************************************/ 77*4882a593Smuzhiyun #define REG_IO_CTRL_1 0x40 78*4882a593Smuzhiyun enum io_ctrl_1_bits { 79*4882a593Smuzhiyun IO_CTRL_1_NMIONERR = BIT(7), 80*4882a593Smuzhiyun IO_CTRL_1_LPC_ERR = BIT(6), 81*4882a593Smuzhiyun IO_CTRL_1_PW2LPC = BIT(1), 82*4882a593Smuzhiyun IO_CTRL_1_CLEAR_MASK = (IO_CTRL_1_LPC_ERR | IO_CTRL_1_PW2LPC) 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /************************************************************ 86*4882a593Smuzhiyun * Legacy I/O Space Registers 87*4882a593Smuzhiyun ************************************************************/ 88*4882a593Smuzhiyun #define REG_AT_COMPAT 0x61 89*4882a593Smuzhiyun enum at_compat_bits { 90*4882a593Smuzhiyun AT_COMPAT_SERR = BIT(7), 91*4882a593Smuzhiyun AT_COMPAT_IOCHK = BIT(6), 92*4882a593Smuzhiyun AT_COMPAT_CLRIOCHK = BIT(3), 93*4882a593Smuzhiyun AT_COMPAT_CLRSERR = BIT(2), 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun struct amd8111_dev_info { 97*4882a593Smuzhiyun u16 err_dev; /* PCI Device ID */ 98*4882a593Smuzhiyun struct pci_dev *dev; 99*4882a593Smuzhiyun int edac_idx; /* device index */ 100*4882a593Smuzhiyun char *ctl_name; 101*4882a593Smuzhiyun struct edac_device_ctl_info *edac_dev; 102*4882a593Smuzhiyun void (*init)(struct amd8111_dev_info *dev_info); 103*4882a593Smuzhiyun void (*exit)(struct amd8111_dev_info *dev_info); 104*4882a593Smuzhiyun void (*check)(struct edac_device_ctl_info *edac_dev); 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun struct amd8111_pci_info { 108*4882a593Smuzhiyun u16 err_dev; /* PCI Device ID */ 109*4882a593Smuzhiyun struct pci_dev *dev; 110*4882a593Smuzhiyun int edac_idx; /* pci index */ 111*4882a593Smuzhiyun const char *ctl_name; 112*4882a593Smuzhiyun struct edac_pci_ctl_info *edac_dev; 113*4882a593Smuzhiyun void (*init)(struct amd8111_pci_info *dev_info); 114*4882a593Smuzhiyun void (*exit)(struct amd8111_pci_info *dev_info); 115*4882a593Smuzhiyun void (*check)(struct edac_pci_ctl_info *edac_dev); 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #endif /* _AMD8111_EDAC_H_ */ 119