1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun #include "amd64_edac.h"
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #define EDAC_DCT_ATTR_SHOW(reg) \
5*4882a593Smuzhiyun static ssize_t amd64_##reg##_show(struct device *dev, \
6*4882a593Smuzhiyun struct device_attribute *mattr, \
7*4882a593Smuzhiyun char *data) \
8*4882a593Smuzhiyun { \
9*4882a593Smuzhiyun struct mem_ctl_info *mci = to_mci(dev); \
10*4882a593Smuzhiyun struct amd64_pvt *pvt = mci->pvt_info; \
11*4882a593Smuzhiyun return sprintf(data, "0x%016llx\n", (u64)pvt->reg); \
12*4882a593Smuzhiyun }
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun EDAC_DCT_ATTR_SHOW(dhar);
15*4882a593Smuzhiyun EDAC_DCT_ATTR_SHOW(dbam0);
16*4882a593Smuzhiyun EDAC_DCT_ATTR_SHOW(top_mem);
17*4882a593Smuzhiyun EDAC_DCT_ATTR_SHOW(top_mem2);
18*4882a593Smuzhiyun
amd64_hole_show(struct device * dev,struct device_attribute * mattr,char * data)19*4882a593Smuzhiyun static ssize_t amd64_hole_show(struct device *dev,
20*4882a593Smuzhiyun struct device_attribute *mattr,
21*4882a593Smuzhiyun char *data)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun struct mem_ctl_info *mci = to_mci(dev);
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun u64 hole_base = 0;
26*4882a593Smuzhiyun u64 hole_offset = 0;
27*4882a593Smuzhiyun u64 hole_size = 0;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun amd64_get_dram_hole_info(mci, &hole_base, &hole_offset, &hole_size);
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun return sprintf(data, "%llx %llx %llx\n", hole_base, hole_offset,
32*4882a593Smuzhiyun hole_size);
33*4882a593Smuzhiyun }
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /*
36*4882a593Smuzhiyun * update NUM_DBG_ATTRS in case you add new members
37*4882a593Smuzhiyun */
38*4882a593Smuzhiyun static DEVICE_ATTR(dhar, S_IRUGO, amd64_dhar_show, NULL);
39*4882a593Smuzhiyun static DEVICE_ATTR(dbam, S_IRUGO, amd64_dbam0_show, NULL);
40*4882a593Smuzhiyun static DEVICE_ATTR(topmem, S_IRUGO, amd64_top_mem_show, NULL);
41*4882a593Smuzhiyun static DEVICE_ATTR(topmem2, S_IRUGO, amd64_top_mem2_show, NULL);
42*4882a593Smuzhiyun static DEVICE_ATTR(dram_hole, S_IRUGO, amd64_hole_show, NULL);
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun static struct attribute *amd64_edac_dbg_attrs[] = {
45*4882a593Smuzhiyun &dev_attr_dhar.attr,
46*4882a593Smuzhiyun &dev_attr_dbam.attr,
47*4882a593Smuzhiyun &dev_attr_topmem.attr,
48*4882a593Smuzhiyun &dev_attr_topmem2.attr,
49*4882a593Smuzhiyun &dev_attr_dram_hole.attr,
50*4882a593Smuzhiyun NULL
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun const struct attribute_group amd64_edac_dbg_group = {
54*4882a593Smuzhiyun .attrs = amd64_edac_dbg_attrs,
55*4882a593Smuzhiyun };
56