xref: /OK3568_Linux_fs/kernel/drivers/dma/ti/k3-psil-am654.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *  Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
4*4882a593Smuzhiyun  *  Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <linux/kernel.h>
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include "k3-psil-priv.h"
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #define PSIL_PDMA_XY_TR(x)				\
12*4882a593Smuzhiyun 	{						\
13*4882a593Smuzhiyun 		.thread_id = x,				\
14*4882a593Smuzhiyun 		.ep_config = {				\
15*4882a593Smuzhiyun 			.ep_type = PSIL_EP_PDMA_XY,	\
16*4882a593Smuzhiyun 		},					\
17*4882a593Smuzhiyun 	}
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #define PSIL_PDMA_XY_PKT(x)				\
20*4882a593Smuzhiyun 	{						\
21*4882a593Smuzhiyun 		.thread_id = x,				\
22*4882a593Smuzhiyun 		.ep_config = {				\
23*4882a593Smuzhiyun 			.ep_type = PSIL_EP_PDMA_XY,	\
24*4882a593Smuzhiyun 			.pkt_mode = 1,			\
25*4882a593Smuzhiyun 		},					\
26*4882a593Smuzhiyun 	}
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #define PSIL_ETHERNET(x)				\
29*4882a593Smuzhiyun 	{						\
30*4882a593Smuzhiyun 		.thread_id = x,				\
31*4882a593Smuzhiyun 		.ep_config = {				\
32*4882a593Smuzhiyun 			.ep_type = PSIL_EP_NATIVE,	\
33*4882a593Smuzhiyun 			.pkt_mode = 1,			\
34*4882a593Smuzhiyun 			.needs_epib = 1,		\
35*4882a593Smuzhiyun 			.psd_size = 16,			\
36*4882a593Smuzhiyun 		},					\
37*4882a593Smuzhiyun 	}
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun #define PSIL_SA2UL(x, tx)				\
40*4882a593Smuzhiyun 	{						\
41*4882a593Smuzhiyun 		.thread_id = x,				\
42*4882a593Smuzhiyun 		.ep_config = {				\
43*4882a593Smuzhiyun 			.ep_type = PSIL_EP_NATIVE,	\
44*4882a593Smuzhiyun 			.pkt_mode = 1,			\
45*4882a593Smuzhiyun 			.needs_epib = 1,		\
46*4882a593Smuzhiyun 			.psd_size = 64,			\
47*4882a593Smuzhiyun 			.notdpkt = tx,			\
48*4882a593Smuzhiyun 		},					\
49*4882a593Smuzhiyun 	}
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun /* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
52*4882a593Smuzhiyun static struct psil_ep am654_src_ep_map[] = {
53*4882a593Smuzhiyun 	/* SA2UL */
54*4882a593Smuzhiyun 	PSIL_SA2UL(0x4000, 0),
55*4882a593Smuzhiyun 	PSIL_SA2UL(0x4001, 0),
56*4882a593Smuzhiyun 	PSIL_SA2UL(0x4002, 0),
57*4882a593Smuzhiyun 	PSIL_SA2UL(0x4003, 0),
58*4882a593Smuzhiyun 	/* PRU_ICSSG0 */
59*4882a593Smuzhiyun 	PSIL_ETHERNET(0x4100),
60*4882a593Smuzhiyun 	PSIL_ETHERNET(0x4101),
61*4882a593Smuzhiyun 	PSIL_ETHERNET(0x4102),
62*4882a593Smuzhiyun 	PSIL_ETHERNET(0x4103),
63*4882a593Smuzhiyun 	/* PRU_ICSSG1 */
64*4882a593Smuzhiyun 	PSIL_ETHERNET(0x4200),
65*4882a593Smuzhiyun 	PSIL_ETHERNET(0x4201),
66*4882a593Smuzhiyun 	PSIL_ETHERNET(0x4202),
67*4882a593Smuzhiyun 	PSIL_ETHERNET(0x4203),
68*4882a593Smuzhiyun 	/* PRU_ICSSG2 */
69*4882a593Smuzhiyun 	PSIL_ETHERNET(0x4300),
70*4882a593Smuzhiyun 	PSIL_ETHERNET(0x4301),
71*4882a593Smuzhiyun 	PSIL_ETHERNET(0x4302),
72*4882a593Smuzhiyun 	PSIL_ETHERNET(0x4303),
73*4882a593Smuzhiyun 	/* PDMA0 - McASPs */
74*4882a593Smuzhiyun 	PSIL_PDMA_XY_TR(0x4400),
75*4882a593Smuzhiyun 	PSIL_PDMA_XY_TR(0x4401),
76*4882a593Smuzhiyun 	PSIL_PDMA_XY_TR(0x4402),
77*4882a593Smuzhiyun 	/* PDMA1 - SPI0-4 */
78*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x4500),
79*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x4501),
80*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x4502),
81*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x4503),
82*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x4504),
83*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x4505),
84*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x4506),
85*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x4507),
86*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x4508),
87*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x4509),
88*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x450a),
89*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x450b),
90*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x450c),
91*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x450d),
92*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x450e),
93*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x450f),
94*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x4510),
95*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x4511),
96*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x4512),
97*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x4513),
98*4882a593Smuzhiyun 	/* PDMA1 - USART0-2 */
99*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x4514),
100*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x4515),
101*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x4516),
102*4882a593Smuzhiyun 	/* CPSW0 */
103*4882a593Smuzhiyun 	PSIL_ETHERNET(0x7000),
104*4882a593Smuzhiyun 	/* MCU_PDMA0 - ADCs */
105*4882a593Smuzhiyun 	PSIL_PDMA_XY_TR(0x7100),
106*4882a593Smuzhiyun 	PSIL_PDMA_XY_TR(0x7101),
107*4882a593Smuzhiyun 	PSIL_PDMA_XY_TR(0x7102),
108*4882a593Smuzhiyun 	PSIL_PDMA_XY_TR(0x7103),
109*4882a593Smuzhiyun 	/* MCU_PDMA1 - MCU_SPI0-2 */
110*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x7200),
111*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x7201),
112*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x7202),
113*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x7203),
114*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x7204),
115*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x7205),
116*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x7206),
117*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x7207),
118*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x7208),
119*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x7209),
120*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x720a),
121*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x720b),
122*4882a593Smuzhiyun 	/* MCU_PDMA1 - MCU_USART0 */
123*4882a593Smuzhiyun 	PSIL_PDMA_XY_PKT(0x7212),
124*4882a593Smuzhiyun };
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun /* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
127*4882a593Smuzhiyun static struct psil_ep am654_dst_ep_map[] = {
128*4882a593Smuzhiyun 	/* SA2UL */
129*4882a593Smuzhiyun 	PSIL_SA2UL(0xc000, 1),
130*4882a593Smuzhiyun 	PSIL_SA2UL(0xc001, 1),
131*4882a593Smuzhiyun 	/* PRU_ICSSG0 */
132*4882a593Smuzhiyun 	PSIL_ETHERNET(0xc100),
133*4882a593Smuzhiyun 	PSIL_ETHERNET(0xc101),
134*4882a593Smuzhiyun 	PSIL_ETHERNET(0xc102),
135*4882a593Smuzhiyun 	PSIL_ETHERNET(0xc103),
136*4882a593Smuzhiyun 	PSIL_ETHERNET(0xc104),
137*4882a593Smuzhiyun 	PSIL_ETHERNET(0xc105),
138*4882a593Smuzhiyun 	PSIL_ETHERNET(0xc106),
139*4882a593Smuzhiyun 	PSIL_ETHERNET(0xc107),
140*4882a593Smuzhiyun 	/* PRU_ICSSG1 */
141*4882a593Smuzhiyun 	PSIL_ETHERNET(0xc200),
142*4882a593Smuzhiyun 	PSIL_ETHERNET(0xc201),
143*4882a593Smuzhiyun 	PSIL_ETHERNET(0xc202),
144*4882a593Smuzhiyun 	PSIL_ETHERNET(0xc203),
145*4882a593Smuzhiyun 	PSIL_ETHERNET(0xc204),
146*4882a593Smuzhiyun 	PSIL_ETHERNET(0xc205),
147*4882a593Smuzhiyun 	PSIL_ETHERNET(0xc206),
148*4882a593Smuzhiyun 	PSIL_ETHERNET(0xc207),
149*4882a593Smuzhiyun 	/* PRU_ICSSG2 */
150*4882a593Smuzhiyun 	PSIL_ETHERNET(0xc300),
151*4882a593Smuzhiyun 	PSIL_ETHERNET(0xc301),
152*4882a593Smuzhiyun 	PSIL_ETHERNET(0xc302),
153*4882a593Smuzhiyun 	PSIL_ETHERNET(0xc303),
154*4882a593Smuzhiyun 	PSIL_ETHERNET(0xc304),
155*4882a593Smuzhiyun 	PSIL_ETHERNET(0xc305),
156*4882a593Smuzhiyun 	PSIL_ETHERNET(0xc306),
157*4882a593Smuzhiyun 	PSIL_ETHERNET(0xc307),
158*4882a593Smuzhiyun 	/* CPSW0 */
159*4882a593Smuzhiyun 	PSIL_ETHERNET(0xf000),
160*4882a593Smuzhiyun 	PSIL_ETHERNET(0xf001),
161*4882a593Smuzhiyun 	PSIL_ETHERNET(0xf002),
162*4882a593Smuzhiyun 	PSIL_ETHERNET(0xf003),
163*4882a593Smuzhiyun 	PSIL_ETHERNET(0xf004),
164*4882a593Smuzhiyun 	PSIL_ETHERNET(0xf005),
165*4882a593Smuzhiyun 	PSIL_ETHERNET(0xf006),
166*4882a593Smuzhiyun 	PSIL_ETHERNET(0xf007),
167*4882a593Smuzhiyun };
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun struct psil_ep_map am654_ep_map = {
170*4882a593Smuzhiyun 	.name = "am654",
171*4882a593Smuzhiyun 	.src = am654_src_ep_map,
172*4882a593Smuzhiyun 	.src_count = ARRAY_SIZE(am654_src_ep_map),
173*4882a593Smuzhiyun 	.dst = am654_dst_ep_map,
174*4882a593Smuzhiyun 	.dst_count = ARRAY_SIZE(am654_dst_ep_map),
175*4882a593Smuzhiyun };
176