1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Renesas SuperH DMA Engine support 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> 6*4882a593Smuzhiyun * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun #ifndef __DMA_SHDMA_H 10*4882a593Smuzhiyun #define __DMA_SHDMA_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/sh_dma.h> 13*4882a593Smuzhiyun #include <linux/shdma-base.h> 14*4882a593Smuzhiyun #include <linux/dmaengine.h> 15*4882a593Smuzhiyun #include <linux/interrupt.h> 16*4882a593Smuzhiyun #include <linux/list.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define SH_DMAE_MAX_CHANNELS 20 19*4882a593Smuzhiyun #define SH_DMAE_TCR_MAX 0x00FFFFFF /* 16MB */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun struct device; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun struct sh_dmae_chan { 24*4882a593Smuzhiyun struct shdma_chan shdma_chan; 25*4882a593Smuzhiyun const struct sh_dmae_slave_config *config; /* Slave DMA configuration */ 26*4882a593Smuzhiyun int xmit_shift; /* log_2(bytes_per_xfer) */ 27*4882a593Smuzhiyun void __iomem *base; 28*4882a593Smuzhiyun char dev_id[16]; /* unique name per DMAC of channel */ 29*4882a593Smuzhiyun int pm_error; 30*4882a593Smuzhiyun dma_addr_t slave_addr; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun struct sh_dmae_device { 34*4882a593Smuzhiyun struct shdma_dev shdma_dev; 35*4882a593Smuzhiyun struct sh_dmae_chan *chan[SH_DMAE_MAX_CHANNELS]; 36*4882a593Smuzhiyun const struct sh_dmae_pdata *pdata; 37*4882a593Smuzhiyun struct list_head node; 38*4882a593Smuzhiyun void __iomem *chan_reg; 39*4882a593Smuzhiyun void __iomem *dmars; 40*4882a593Smuzhiyun unsigned int chcr_offset; 41*4882a593Smuzhiyun u32 chcr_ie_bit; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun struct sh_dmae_regs { 45*4882a593Smuzhiyun u32 sar; /* SAR / source address */ 46*4882a593Smuzhiyun u32 dar; /* DAR / destination address */ 47*4882a593Smuzhiyun u32 tcr; /* TCR / transfer count */ 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun struct sh_dmae_desc { 51*4882a593Smuzhiyun struct sh_dmae_regs hw; 52*4882a593Smuzhiyun struct shdma_desc shdma_desc; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define to_sh_chan(chan) container_of(chan, struct sh_dmae_chan, shdma_chan) 56*4882a593Smuzhiyun #define to_sh_desc(lh) container_of(lh, struct sh_desc, node) 57*4882a593Smuzhiyun #define tx_to_sh_desc(tx) container_of(tx, struct sh_desc, async_tx) 58*4882a593Smuzhiyun #define to_sh_dev(chan) container_of(chan->shdma_chan.dma_chan.device,\ 59*4882a593Smuzhiyun struct sh_dmae_device, shdma_dev.dma_dev) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #endif /* __DMA_SHDMA_H */ 62