xref: /OK3568_Linux_fs/kernel/drivers/dma/qcom/hidma_dbg.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Qualcomm Technologies HIDMA debug file
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/debugfs.h>
9*4882a593Smuzhiyun #include <linux/device.h>
10*4882a593Smuzhiyun #include <linux/list.h>
11*4882a593Smuzhiyun #include <linux/pm_runtime.h>
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #include "hidma.h"
14*4882a593Smuzhiyun 
hidma_ll_chstats(struct seq_file * s,void * llhndl,u32 tre_ch)15*4882a593Smuzhiyun static void hidma_ll_chstats(struct seq_file *s, void *llhndl, u32 tre_ch)
16*4882a593Smuzhiyun {
17*4882a593Smuzhiyun 	struct hidma_lldev *lldev = llhndl;
18*4882a593Smuzhiyun 	struct hidma_tre *tre;
19*4882a593Smuzhiyun 	u32 length;
20*4882a593Smuzhiyun 	dma_addr_t src_start;
21*4882a593Smuzhiyun 	dma_addr_t dest_start;
22*4882a593Smuzhiyun 	u32 *tre_local;
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun 	if (tre_ch >= lldev->nr_tres) {
25*4882a593Smuzhiyun 		dev_err(lldev->dev, "invalid TRE number in chstats:%d", tre_ch);
26*4882a593Smuzhiyun 		return;
27*4882a593Smuzhiyun 	}
28*4882a593Smuzhiyun 	tre = &lldev->trepool[tre_ch];
29*4882a593Smuzhiyun 	seq_printf(s, "------Channel %d -----\n", tre_ch);
30*4882a593Smuzhiyun 	seq_printf(s, "allocated=%d\n", atomic_read(&tre->allocated));
31*4882a593Smuzhiyun 	seq_printf(s, "queued = 0x%x\n", tre->queued);
32*4882a593Smuzhiyun 	seq_printf(s, "err_info = 0x%x\n", tre->err_info);
33*4882a593Smuzhiyun 	seq_printf(s, "err_code = 0x%x\n", tre->err_code);
34*4882a593Smuzhiyun 	seq_printf(s, "status = 0x%x\n", tre->status);
35*4882a593Smuzhiyun 	seq_printf(s, "idx = 0x%x\n", tre->idx);
36*4882a593Smuzhiyun 	seq_printf(s, "dma_sig = 0x%x\n", tre->dma_sig);
37*4882a593Smuzhiyun 	seq_printf(s, "dev_name=%s\n", tre->dev_name);
38*4882a593Smuzhiyun 	seq_printf(s, "callback=%p\n", tre->callback);
39*4882a593Smuzhiyun 	seq_printf(s, "data=%p\n", tre->data);
40*4882a593Smuzhiyun 	seq_printf(s, "tre_index = 0x%x\n", tre->tre_index);
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun 	tre_local = &tre->tre_local[0];
43*4882a593Smuzhiyun 	src_start = tre_local[HIDMA_TRE_SRC_LOW_IDX];
44*4882a593Smuzhiyun 	src_start = ((u64) (tre_local[HIDMA_TRE_SRC_HI_IDX]) << 32) + src_start;
45*4882a593Smuzhiyun 	dest_start = tre_local[HIDMA_TRE_DEST_LOW_IDX];
46*4882a593Smuzhiyun 	dest_start += ((u64) (tre_local[HIDMA_TRE_DEST_HI_IDX]) << 32);
47*4882a593Smuzhiyun 	length = tre_local[HIDMA_TRE_LEN_IDX];
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun 	seq_printf(s, "src=%pap\n", &src_start);
50*4882a593Smuzhiyun 	seq_printf(s, "dest=%pap\n", &dest_start);
51*4882a593Smuzhiyun 	seq_printf(s, "length = 0x%x\n", length);
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun 
hidma_ll_devstats(struct seq_file * s,void * llhndl)54*4882a593Smuzhiyun static void hidma_ll_devstats(struct seq_file *s, void *llhndl)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun 	struct hidma_lldev *lldev = llhndl;
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun 	seq_puts(s, "------Device -----\n");
59*4882a593Smuzhiyun 	seq_printf(s, "lldev init = 0x%x\n", lldev->initialized);
60*4882a593Smuzhiyun 	seq_printf(s, "trch_state = 0x%x\n", lldev->trch_state);
61*4882a593Smuzhiyun 	seq_printf(s, "evch_state = 0x%x\n", lldev->evch_state);
62*4882a593Smuzhiyun 	seq_printf(s, "chidx = 0x%x\n", lldev->chidx);
63*4882a593Smuzhiyun 	seq_printf(s, "nr_tres = 0x%x\n", lldev->nr_tres);
64*4882a593Smuzhiyun 	seq_printf(s, "trca=%p\n", lldev->trca);
65*4882a593Smuzhiyun 	seq_printf(s, "tre_ring=%p\n", lldev->tre_ring);
66*4882a593Smuzhiyun 	seq_printf(s, "tre_ring_handle=%pap\n", &lldev->tre_dma);
67*4882a593Smuzhiyun 	seq_printf(s, "tre_ring_size = 0x%x\n", lldev->tre_ring_size);
68*4882a593Smuzhiyun 	seq_printf(s, "tre_processed_off = 0x%x\n", lldev->tre_processed_off);
69*4882a593Smuzhiyun 	seq_printf(s, "pending_tre_count=%d\n",
70*4882a593Smuzhiyun 			atomic_read(&lldev->pending_tre_count));
71*4882a593Smuzhiyun 	seq_printf(s, "evca=%p\n", lldev->evca);
72*4882a593Smuzhiyun 	seq_printf(s, "evre_ring=%p\n", lldev->evre_ring);
73*4882a593Smuzhiyun 	seq_printf(s, "evre_ring_handle=%pap\n", &lldev->evre_dma);
74*4882a593Smuzhiyun 	seq_printf(s, "evre_ring_size = 0x%x\n", lldev->evre_ring_size);
75*4882a593Smuzhiyun 	seq_printf(s, "evre_processed_off = 0x%x\n", lldev->evre_processed_off);
76*4882a593Smuzhiyun 	seq_printf(s, "tre_write_offset = 0x%x\n", lldev->tre_write_offset);
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun /*
80*4882a593Smuzhiyun  * hidma_chan_show: display HIDMA channel statistics
81*4882a593Smuzhiyun  *
82*4882a593Smuzhiyun  * Display the statistics for the current HIDMA virtual channel device.
83*4882a593Smuzhiyun  */
hidma_chan_show(struct seq_file * s,void * unused)84*4882a593Smuzhiyun static int hidma_chan_show(struct seq_file *s, void *unused)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun 	struct hidma_chan *mchan = s->private;
87*4882a593Smuzhiyun 	struct hidma_desc *mdesc;
88*4882a593Smuzhiyun 	struct hidma_dev *dmadev = mchan->dmadev;
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	pm_runtime_get_sync(dmadev->ddev.dev);
91*4882a593Smuzhiyun 	seq_printf(s, "paused=%u\n", mchan->paused);
92*4882a593Smuzhiyun 	seq_printf(s, "dma_sig=%u\n", mchan->dma_sig);
93*4882a593Smuzhiyun 	seq_puts(s, "prepared\n");
94*4882a593Smuzhiyun 	list_for_each_entry(mdesc, &mchan->prepared, node)
95*4882a593Smuzhiyun 		hidma_ll_chstats(s, mchan->dmadev->lldev, mdesc->tre_ch);
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 	seq_puts(s, "active\n");
98*4882a593Smuzhiyun 	list_for_each_entry(mdesc, &mchan->active, node)
99*4882a593Smuzhiyun 		hidma_ll_chstats(s, mchan->dmadev->lldev, mdesc->tre_ch);
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 	seq_puts(s, "completed\n");
102*4882a593Smuzhiyun 	list_for_each_entry(mdesc, &mchan->completed, node)
103*4882a593Smuzhiyun 		hidma_ll_chstats(s, mchan->dmadev->lldev, mdesc->tre_ch);
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	hidma_ll_devstats(s, mchan->dmadev->lldev);
106*4882a593Smuzhiyun 	pm_runtime_mark_last_busy(dmadev->ddev.dev);
107*4882a593Smuzhiyun 	pm_runtime_put_autosuspend(dmadev->ddev.dev);
108*4882a593Smuzhiyun 	return 0;
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun /*
112*4882a593Smuzhiyun  * hidma_dma_show: display HIDMA device info
113*4882a593Smuzhiyun  *
114*4882a593Smuzhiyun  * Display the info for the current HIDMA device.
115*4882a593Smuzhiyun  */
hidma_dma_show(struct seq_file * s,void * unused)116*4882a593Smuzhiyun static int hidma_dma_show(struct seq_file *s, void *unused)
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun 	struct hidma_dev *dmadev = s->private;
119*4882a593Smuzhiyun 	resource_size_t sz;
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 	seq_printf(s, "nr_descriptors=%d\n", dmadev->nr_descriptors);
122*4882a593Smuzhiyun 	seq_printf(s, "dev_trca=%p\n", &dmadev->dev_trca);
123*4882a593Smuzhiyun 	seq_printf(s, "dev_trca_phys=%pa\n", &dmadev->trca_resource->start);
124*4882a593Smuzhiyun 	sz = resource_size(dmadev->trca_resource);
125*4882a593Smuzhiyun 	seq_printf(s, "dev_trca_size=%pa\n", &sz);
126*4882a593Smuzhiyun 	seq_printf(s, "dev_evca=%p\n", &dmadev->dev_evca);
127*4882a593Smuzhiyun 	seq_printf(s, "dev_evca_phys=%pa\n", &dmadev->evca_resource->start);
128*4882a593Smuzhiyun 	sz = resource_size(dmadev->evca_resource);
129*4882a593Smuzhiyun 	seq_printf(s, "dev_evca_size=%pa\n", &sz);
130*4882a593Smuzhiyun 	return 0;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun DEFINE_SHOW_ATTRIBUTE(hidma_chan);
134*4882a593Smuzhiyun DEFINE_SHOW_ATTRIBUTE(hidma_dma);
135*4882a593Smuzhiyun 
hidma_debug_uninit(struct hidma_dev * dmadev)136*4882a593Smuzhiyun void hidma_debug_uninit(struct hidma_dev *dmadev)
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun 	debugfs_remove_recursive(dmadev->debugfs);
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun 
hidma_debug_init(struct hidma_dev * dmadev)141*4882a593Smuzhiyun void hidma_debug_init(struct hidma_dev *dmadev)
142*4882a593Smuzhiyun {
143*4882a593Smuzhiyun 	int chidx = 0;
144*4882a593Smuzhiyun 	struct list_head *position = NULL;
145*4882a593Smuzhiyun 	struct dentry *dir;
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	dmadev->debugfs = debugfs_create_dir(dev_name(dmadev->ddev.dev), NULL);
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 	/* walk through the virtual channel list */
150*4882a593Smuzhiyun 	list_for_each(position, &dmadev->ddev.channels) {
151*4882a593Smuzhiyun 		struct hidma_chan *chan;
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun 		chan = list_entry(position, struct hidma_chan,
154*4882a593Smuzhiyun 				  chan.device_node);
155*4882a593Smuzhiyun 		sprintf(chan->dbg_name, "chan%d", chidx);
156*4882a593Smuzhiyun 		dir = debugfs_create_dir(chan->dbg_name,
157*4882a593Smuzhiyun 						   dmadev->debugfs);
158*4882a593Smuzhiyun 		debugfs_create_file("stats", S_IRUGO, dir, chan,
159*4882a593Smuzhiyun 				    &hidma_chan_fops);
160*4882a593Smuzhiyun 		chidx++;
161*4882a593Smuzhiyun 	}
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	debugfs_create_file("stats", S_IRUGO, dmadev->debugfs, dmadev,
164*4882a593Smuzhiyun 			    &hidma_dma_fops);
165*4882a593Smuzhiyun }
166