1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * 440SPe's XOR engines support header file 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * 2006-2009 (C) DENX Software Engineering. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Author: Yuri Tikhonov <yur@emcraft.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * This file is licensed under the term of the GNU General Public License 9*4882a593Smuzhiyun * version 2. The program licensed "as is" without any warranty of any 10*4882a593Smuzhiyun * kind, whether express or implied. 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef _PPC440SPE_XOR_H 14*4882a593Smuzhiyun #define _PPC440SPE_XOR_H 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #include <linux/types.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* Number of XOR engines available on the contoller */ 19*4882a593Smuzhiyun #define XOR_ENGINES_NUM 1 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* Number of operands supported in the h/w */ 22*4882a593Smuzhiyun #define XOR_MAX_OPS 16 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* 25*4882a593Smuzhiyun * XOR Command Block Control Register bits 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun #define XOR_CBCR_LNK_BIT (1<<31) /* link present */ 28*4882a593Smuzhiyun #define XOR_CBCR_TGT_BIT (1<<30) /* target present */ 29*4882a593Smuzhiyun #define XOR_CBCR_CBCE_BIT (1<<29) /* command block compete enable */ 30*4882a593Smuzhiyun #define XOR_CBCR_RNZE_BIT (1<<28) /* result not zero enable */ 31*4882a593Smuzhiyun #define XOR_CBCR_XNOR_BIT (1<<15) /* XOR/XNOR */ 32*4882a593Smuzhiyun #define XOR_CDCR_OAC_MSK (0x7F) /* operand address count */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* 35*4882a593Smuzhiyun * XORCore Status Register bits 36*4882a593Smuzhiyun */ 37*4882a593Smuzhiyun #define XOR_SR_XCP_BIT (1<<31) /* core processing */ 38*4882a593Smuzhiyun #define XOR_SR_ICB_BIT (1<<17) /* invalid CB */ 39*4882a593Smuzhiyun #define XOR_SR_IC_BIT (1<<16) /* invalid command */ 40*4882a593Smuzhiyun #define XOR_SR_IPE_BIT (1<<15) /* internal parity error */ 41*4882a593Smuzhiyun #define XOR_SR_RNZ_BIT (1<<2) /* result not Zero */ 42*4882a593Smuzhiyun #define XOR_SR_CBC_BIT (1<<1) /* CB complete */ 43*4882a593Smuzhiyun #define XOR_SR_CBLC_BIT (1<<0) /* CB list complete */ 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* 46*4882a593Smuzhiyun * XORCore Control Set and Reset Register bits 47*4882a593Smuzhiyun */ 48*4882a593Smuzhiyun #define XOR_CRSR_XASR_BIT (1<<31) /* soft reset */ 49*4882a593Smuzhiyun #define XOR_CRSR_XAE_BIT (1<<30) /* enable */ 50*4882a593Smuzhiyun #define XOR_CRSR_RCBE_BIT (1<<29) /* refetch CB enable */ 51*4882a593Smuzhiyun #define XOR_CRSR_PAUS_BIT (1<<28) /* pause */ 52*4882a593Smuzhiyun #define XOR_CRSR_64BA_BIT (1<<27) /* 64/32 CB format */ 53*4882a593Smuzhiyun #define XOR_CRSR_CLP_BIT (1<<25) /* continue list processing */ 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* 56*4882a593Smuzhiyun * XORCore Interrupt Enable Register 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun #define XOR_IE_ICBIE_BIT (1<<17) /* Invalid Command Block IRQ Enable */ 59*4882a593Smuzhiyun #define XOR_IE_ICIE_BIT (1<<16) /* Invalid Command IRQ Enable */ 60*4882a593Smuzhiyun #define XOR_IE_RPTIE_BIT (1<<14) /* Read PLB Timeout Error IRQ Enable */ 61*4882a593Smuzhiyun #define XOR_IE_CBCIE_BIT (1<<1) /* CB complete interrupt enable */ 62*4882a593Smuzhiyun #define XOR_IE_CBLCI_BIT (1<<0) /* CB list complete interrupt enable */ 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* 65*4882a593Smuzhiyun * XOR Accelerator engine Command Block Type 66*4882a593Smuzhiyun */ 67*4882a593Smuzhiyun struct xor_cb { 68*4882a593Smuzhiyun /* 69*4882a593Smuzhiyun * Basic 64-bit format XOR CB (Table 19-1, p.463, 440spe_um_1_22.pdf) 70*4882a593Smuzhiyun */ 71*4882a593Smuzhiyun u32 cbc; /* control */ 72*4882a593Smuzhiyun u32 cbbc; /* byte count */ 73*4882a593Smuzhiyun u32 cbs; /* status */ 74*4882a593Smuzhiyun u8 pad0[4]; /* reserved */ 75*4882a593Smuzhiyun u32 cbtah; /* target address high */ 76*4882a593Smuzhiyun u32 cbtal; /* target address low */ 77*4882a593Smuzhiyun u32 cblah; /* link address high */ 78*4882a593Smuzhiyun u32 cblal; /* link address low */ 79*4882a593Smuzhiyun struct { 80*4882a593Smuzhiyun u32 h; 81*4882a593Smuzhiyun u32 l; 82*4882a593Smuzhiyun } __attribute__ ((packed)) ops[16]; 83*4882a593Smuzhiyun } __attribute__ ((packed)); 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* 86*4882a593Smuzhiyun * XOR hardware registers Table 19-3, UM 1.22 87*4882a593Smuzhiyun */ 88*4882a593Smuzhiyun struct xor_regs { 89*4882a593Smuzhiyun u32 op_ar[16][2]; /* operand address[0]-high,[1]-low registers */ 90*4882a593Smuzhiyun u8 pad0[352]; /* reserved */ 91*4882a593Smuzhiyun u32 cbcr; /* CB control register */ 92*4882a593Smuzhiyun u32 cbbcr; /* CB byte count register */ 93*4882a593Smuzhiyun u32 cbsr; /* CB status register */ 94*4882a593Smuzhiyun u8 pad1[4]; /* reserved */ 95*4882a593Smuzhiyun u32 cbtahr; /* operand target address high register */ 96*4882a593Smuzhiyun u32 cbtalr; /* operand target address low register */ 97*4882a593Smuzhiyun u32 cblahr; /* CB link address high register */ 98*4882a593Smuzhiyun u32 cblalr; /* CB link address low register */ 99*4882a593Smuzhiyun u32 crsr; /* control set register */ 100*4882a593Smuzhiyun u32 crrr; /* control reset register */ 101*4882a593Smuzhiyun u32 ccbahr; /* current CB address high register */ 102*4882a593Smuzhiyun u32 ccbalr; /* current CB address low register */ 103*4882a593Smuzhiyun u32 plbr; /* PLB configuration register */ 104*4882a593Smuzhiyun u32 ier; /* interrupt enable register */ 105*4882a593Smuzhiyun u32 pecr; /* parity error count register */ 106*4882a593Smuzhiyun u32 sr; /* status register */ 107*4882a593Smuzhiyun u32 revidr; /* revision ID register */ 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun #endif /* _PPC440SPE_XOR_H */ 111