1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun 3*4882a593Smuzhiyunconfig MTK_HSDMA 4*4882a593Smuzhiyun tristate "MediaTek High-Speed DMA controller support" 5*4882a593Smuzhiyun depends on ARCH_MEDIATEK || COMPILE_TEST 6*4882a593Smuzhiyun select DMA_ENGINE 7*4882a593Smuzhiyun select DMA_VIRTUAL_CHANNELS 8*4882a593Smuzhiyun help 9*4882a593Smuzhiyun Enable support for High-Speed DMA controller on MediaTek 10*4882a593Smuzhiyun SoCs. 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun This controller provides the channels which is dedicated to 13*4882a593Smuzhiyun memory-to-memory transfer to offload from CPU through ring- 14*4882a593Smuzhiyun based descriptor management. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyunconfig MTK_CQDMA 17*4882a593Smuzhiyun tristate "MediaTek Command-Queue DMA controller support" 18*4882a593Smuzhiyun depends on ARCH_MEDIATEK || COMPILE_TEST 19*4882a593Smuzhiyun select DMA_ENGINE 20*4882a593Smuzhiyun select DMA_VIRTUAL_CHANNELS 21*4882a593Smuzhiyun select ASYNC_TX_ENABLE_CHANNEL_SWITCH 22*4882a593Smuzhiyun help 23*4882a593Smuzhiyun Enable support for Command-Queue DMA controller on MediaTek 24*4882a593Smuzhiyun SoCs. 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun This controller provides the channels which is dedicated to 27*4882a593Smuzhiyun memory-to-memory transfer to offload from CPU. 28*4882a593Smuzhiyun 29*4882a593Smuzhiyunconfig MTK_UART_APDMA 30*4882a593Smuzhiyun tristate "MediaTek SoCs APDMA support for UART" 31*4882a593Smuzhiyun depends on OF && SERIAL_8250_MT6577 32*4882a593Smuzhiyun select DMA_ENGINE 33*4882a593Smuzhiyun select DMA_VIRTUAL_CHANNELS 34*4882a593Smuzhiyun help 35*4882a593Smuzhiyun Support for the UART DMA engine found on MediaTek MTK SoCs. 36*4882a593Smuzhiyun When SERIAL_8250_MT6577 is enabled, and if you want to use DMA, 37*4882a593Smuzhiyun you can enable the config. The DMA engine can only be used 38*4882a593Smuzhiyun with MediaTek SoCs. 39