1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2008 4*4882a593Smuzhiyun * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _IPU_INTERN_H_ 10*4882a593Smuzhiyun #define _IPU_INTERN_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/dmaengine.h> 13*4882a593Smuzhiyun #include <linux/platform_device.h> 14*4882a593Smuzhiyun #include <linux/interrupt.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* IPU Common registers */ 17*4882a593Smuzhiyun #define IPU_CONF 0x00 18*4882a593Smuzhiyun #define IPU_CHA_BUF0_RDY 0x04 19*4882a593Smuzhiyun #define IPU_CHA_BUF1_RDY 0x08 20*4882a593Smuzhiyun #define IPU_CHA_DB_MODE_SEL 0x0C 21*4882a593Smuzhiyun #define IPU_CHA_CUR_BUF 0x10 22*4882a593Smuzhiyun #define IPU_FS_PROC_FLOW 0x14 23*4882a593Smuzhiyun #define IPU_FS_DISP_FLOW 0x18 24*4882a593Smuzhiyun #define IPU_TASKS_STAT 0x1C 25*4882a593Smuzhiyun #define IPU_IMA_ADDR 0x20 26*4882a593Smuzhiyun #define IPU_IMA_DATA 0x24 27*4882a593Smuzhiyun #define IPU_INT_CTRL_1 0x28 28*4882a593Smuzhiyun #define IPU_INT_CTRL_2 0x2C 29*4882a593Smuzhiyun #define IPU_INT_CTRL_3 0x30 30*4882a593Smuzhiyun #define IPU_INT_CTRL_4 0x34 31*4882a593Smuzhiyun #define IPU_INT_CTRL_5 0x38 32*4882a593Smuzhiyun #define IPU_INT_STAT_1 0x3C 33*4882a593Smuzhiyun #define IPU_INT_STAT_2 0x40 34*4882a593Smuzhiyun #define IPU_INT_STAT_3 0x44 35*4882a593Smuzhiyun #define IPU_INT_STAT_4 0x48 36*4882a593Smuzhiyun #define IPU_INT_STAT_5 0x4C 37*4882a593Smuzhiyun #define IPU_BRK_CTRL_1 0x50 38*4882a593Smuzhiyun #define IPU_BRK_CTRL_2 0x54 39*4882a593Smuzhiyun #define IPU_BRK_STAT 0x58 40*4882a593Smuzhiyun #define IPU_DIAGB_CTRL 0x5C 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* IPU_CONF Register bits */ 43*4882a593Smuzhiyun #define IPU_CONF_CSI_EN 0x00000001 44*4882a593Smuzhiyun #define IPU_CONF_IC_EN 0x00000002 45*4882a593Smuzhiyun #define IPU_CONF_ROT_EN 0x00000004 46*4882a593Smuzhiyun #define IPU_CONF_PF_EN 0x00000008 47*4882a593Smuzhiyun #define IPU_CONF_SDC_EN 0x00000010 48*4882a593Smuzhiyun #define IPU_CONF_ADC_EN 0x00000020 49*4882a593Smuzhiyun #define IPU_CONF_DI_EN 0x00000040 50*4882a593Smuzhiyun #define IPU_CONF_DU_EN 0x00000080 51*4882a593Smuzhiyun #define IPU_CONF_PXL_ENDIAN 0x00000100 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* Image Converter Registers */ 54*4882a593Smuzhiyun #define IC_CONF 0x88 55*4882a593Smuzhiyun #define IC_PRP_ENC_RSC 0x8C 56*4882a593Smuzhiyun #define IC_PRP_VF_RSC 0x90 57*4882a593Smuzhiyun #define IC_PP_RSC 0x94 58*4882a593Smuzhiyun #define IC_CMBP_1 0x98 59*4882a593Smuzhiyun #define IC_CMBP_2 0x9C 60*4882a593Smuzhiyun #define PF_CONF 0xA0 61*4882a593Smuzhiyun #define IDMAC_CONF 0xA4 62*4882a593Smuzhiyun #define IDMAC_CHA_EN 0xA8 63*4882a593Smuzhiyun #define IDMAC_CHA_PRI 0xAC 64*4882a593Smuzhiyun #define IDMAC_CHA_BUSY 0xB0 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* Image Converter Register bits */ 67*4882a593Smuzhiyun #define IC_CONF_PRPENC_EN 0x00000001 68*4882a593Smuzhiyun #define IC_CONF_PRPENC_CSC1 0x00000002 69*4882a593Smuzhiyun #define IC_CONF_PRPENC_ROT_EN 0x00000004 70*4882a593Smuzhiyun #define IC_CONF_PRPVF_EN 0x00000100 71*4882a593Smuzhiyun #define IC_CONF_PRPVF_CSC1 0x00000200 72*4882a593Smuzhiyun #define IC_CONF_PRPVF_CSC2 0x00000400 73*4882a593Smuzhiyun #define IC_CONF_PRPVF_CMB 0x00000800 74*4882a593Smuzhiyun #define IC_CONF_PRPVF_ROT_EN 0x00001000 75*4882a593Smuzhiyun #define IC_CONF_PP_EN 0x00010000 76*4882a593Smuzhiyun #define IC_CONF_PP_CSC1 0x00020000 77*4882a593Smuzhiyun #define IC_CONF_PP_CSC2 0x00040000 78*4882a593Smuzhiyun #define IC_CONF_PP_CMB 0x00080000 79*4882a593Smuzhiyun #define IC_CONF_PP_ROT_EN 0x00100000 80*4882a593Smuzhiyun #define IC_CONF_IC_GLB_LOC_A 0x10000000 81*4882a593Smuzhiyun #define IC_CONF_KEY_COLOR_EN 0x20000000 82*4882a593Smuzhiyun #define IC_CONF_RWS_EN 0x40000000 83*4882a593Smuzhiyun #define IC_CONF_CSI_MEM_WR_EN 0x80000000 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define IDMA_CHAN_INVALID 0x000000FF 86*4882a593Smuzhiyun #define IDMA_IC_0 0x00000001 87*4882a593Smuzhiyun #define IDMA_IC_1 0x00000002 88*4882a593Smuzhiyun #define IDMA_IC_2 0x00000004 89*4882a593Smuzhiyun #define IDMA_IC_3 0x00000008 90*4882a593Smuzhiyun #define IDMA_IC_4 0x00000010 91*4882a593Smuzhiyun #define IDMA_IC_5 0x00000020 92*4882a593Smuzhiyun #define IDMA_IC_6 0x00000040 93*4882a593Smuzhiyun #define IDMA_IC_7 0x00000080 94*4882a593Smuzhiyun #define IDMA_IC_8 0x00000100 95*4882a593Smuzhiyun #define IDMA_IC_9 0x00000200 96*4882a593Smuzhiyun #define IDMA_IC_10 0x00000400 97*4882a593Smuzhiyun #define IDMA_IC_11 0x00000800 98*4882a593Smuzhiyun #define IDMA_IC_12 0x00001000 99*4882a593Smuzhiyun #define IDMA_IC_13 0x00002000 100*4882a593Smuzhiyun #define IDMA_SDC_BG 0x00004000 101*4882a593Smuzhiyun #define IDMA_SDC_FG 0x00008000 102*4882a593Smuzhiyun #define IDMA_SDC_MASK 0x00010000 103*4882a593Smuzhiyun #define IDMA_SDC_PARTIAL 0x00020000 104*4882a593Smuzhiyun #define IDMA_ADC_SYS1_WR 0x00040000 105*4882a593Smuzhiyun #define IDMA_ADC_SYS2_WR 0x00080000 106*4882a593Smuzhiyun #define IDMA_ADC_SYS1_CMD 0x00100000 107*4882a593Smuzhiyun #define IDMA_ADC_SYS2_CMD 0x00200000 108*4882a593Smuzhiyun #define IDMA_ADC_SYS1_RD 0x00400000 109*4882a593Smuzhiyun #define IDMA_ADC_SYS2_RD 0x00800000 110*4882a593Smuzhiyun #define IDMA_PF_QP 0x01000000 111*4882a593Smuzhiyun #define IDMA_PF_BSP 0x02000000 112*4882a593Smuzhiyun #define IDMA_PF_Y_IN 0x04000000 113*4882a593Smuzhiyun #define IDMA_PF_U_IN 0x08000000 114*4882a593Smuzhiyun #define IDMA_PF_V_IN 0x10000000 115*4882a593Smuzhiyun #define IDMA_PF_Y_OUT 0x20000000 116*4882a593Smuzhiyun #define IDMA_PF_U_OUT 0x40000000 117*4882a593Smuzhiyun #define IDMA_PF_V_OUT 0x80000000 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define TSTAT_PF_H264_PAUSE 0x00000001 120*4882a593Smuzhiyun #define TSTAT_CSI2MEM_MASK 0x0000000C 121*4882a593Smuzhiyun #define TSTAT_CSI2MEM_OFFSET 2 122*4882a593Smuzhiyun #define TSTAT_VF_MASK 0x00000600 123*4882a593Smuzhiyun #define TSTAT_VF_OFFSET 9 124*4882a593Smuzhiyun #define TSTAT_VF_ROT_MASK 0x000C0000 125*4882a593Smuzhiyun #define TSTAT_VF_ROT_OFFSET 18 126*4882a593Smuzhiyun #define TSTAT_ENC_MASK 0x00000180 127*4882a593Smuzhiyun #define TSTAT_ENC_OFFSET 7 128*4882a593Smuzhiyun #define TSTAT_ENC_ROT_MASK 0x00030000 129*4882a593Smuzhiyun #define TSTAT_ENC_ROT_OFFSET 16 130*4882a593Smuzhiyun #define TSTAT_PP_MASK 0x00001800 131*4882a593Smuzhiyun #define TSTAT_PP_OFFSET 11 132*4882a593Smuzhiyun #define TSTAT_PP_ROT_MASK 0x00300000 133*4882a593Smuzhiyun #define TSTAT_PP_ROT_OFFSET 20 134*4882a593Smuzhiyun #define TSTAT_PF_MASK 0x00C00000 135*4882a593Smuzhiyun #define TSTAT_PF_OFFSET 22 136*4882a593Smuzhiyun #define TSTAT_ADCSYS1_MASK 0x03000000 137*4882a593Smuzhiyun #define TSTAT_ADCSYS1_OFFSET 24 138*4882a593Smuzhiyun #define TSTAT_ADCSYS2_MASK 0x0C000000 139*4882a593Smuzhiyun #define TSTAT_ADCSYS2_OFFSET 26 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #define TASK_STAT_IDLE 0 142*4882a593Smuzhiyun #define TASK_STAT_ACTIVE 1 143*4882a593Smuzhiyun #define TASK_STAT_WAIT4READY 2 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun struct idmac { 146*4882a593Smuzhiyun struct dma_device dma; 147*4882a593Smuzhiyun }; 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun struct ipu { 150*4882a593Smuzhiyun void __iomem *reg_ipu; 151*4882a593Smuzhiyun void __iomem *reg_ic; 152*4882a593Smuzhiyun unsigned int irq_fn; /* IPU Function IRQ to the CPU */ 153*4882a593Smuzhiyun unsigned int irq_err; /* IPU Error IRQ to the CPU */ 154*4882a593Smuzhiyun unsigned int irq_base; /* Beginning of the IPU IRQ range */ 155*4882a593Smuzhiyun unsigned long channel_init_mask; 156*4882a593Smuzhiyun spinlock_t lock; 157*4882a593Smuzhiyun struct clk *ipu_clk; 158*4882a593Smuzhiyun struct device *dev; 159*4882a593Smuzhiyun struct idmac idmac; 160*4882a593Smuzhiyun struct idmac_channel channel[IPU_CHANNELS_NUM]; 161*4882a593Smuzhiyun struct tasklet_struct tasklet; 162*4882a593Smuzhiyun }; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun #define to_idmac(d) container_of(d, struct idmac, dma) 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun extern int ipu_irq_attach_irq(struct ipu *ipu, struct platform_device *dev); 167*4882a593Smuzhiyun extern void ipu_irq_detach_irq(struct ipu *ipu, struct platform_device *dev); 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun extern bool ipu_irq_status(uint32_t irq); 170*4882a593Smuzhiyun extern int ipu_irq_map(unsigned int source); 171*4882a593Smuzhiyun extern int ipu_irq_unmap(unsigned int source); 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun #endif 174