1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef _IOAT_REGISTERS_H_ 6*4882a593Smuzhiyun #define _IOAT_REGISTERS_H_ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #define IOAT_PCI_DMACTRL_OFFSET 0x48 9*4882a593Smuzhiyun #define IOAT_PCI_DMACTRL_DMA_EN 0x00000001 10*4882a593Smuzhiyun #define IOAT_PCI_DMACTRL_MSI_EN 0x00000002 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define IOAT_PCI_DEVICE_ID_OFFSET 0x02 13*4882a593Smuzhiyun #define IOAT_PCI_DMAUNCERRSTS_OFFSET 0x148 14*4882a593Smuzhiyun #define IOAT_PCI_CHANERR_INT_OFFSET 0x180 15*4882a593Smuzhiyun #define IOAT_PCI_CHANERRMASK_INT_OFFSET 0x184 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* PCIe config registers */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* EXPCAPID + N */ 20*4882a593Smuzhiyun #define IOAT_DEVCTRL_OFFSET 0x8 21*4882a593Smuzhiyun /* relaxed ordering enable */ 22*4882a593Smuzhiyun #define IOAT_DEVCTRL_ROE 0x10 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* MMIO Device Registers */ 25*4882a593Smuzhiyun #define IOAT_CHANCNT_OFFSET 0x00 /* 8-bit */ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define IOAT_XFERCAP_OFFSET 0x01 /* 8-bit */ 28*4882a593Smuzhiyun #define IOAT_XFERCAP_4KB 12 29*4882a593Smuzhiyun #define IOAT_XFERCAP_8KB 13 30*4882a593Smuzhiyun #define IOAT_XFERCAP_16KB 14 31*4882a593Smuzhiyun #define IOAT_XFERCAP_32KB 15 32*4882a593Smuzhiyun #define IOAT_XFERCAP_32GB 0 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define IOAT_GENCTRL_OFFSET 0x02 /* 8-bit */ 35*4882a593Smuzhiyun #define IOAT_GENCTRL_DEBUG_EN 0x01 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define IOAT_INTRCTRL_OFFSET 0x03 /* 8-bit */ 38*4882a593Smuzhiyun #define IOAT_INTRCTRL_MASTER_INT_EN 0x01 /* Master Interrupt Enable */ 39*4882a593Smuzhiyun #define IOAT_INTRCTRL_INT_STATUS 0x02 /* ATTNSTATUS -or- Channel Int */ 40*4882a593Smuzhiyun #define IOAT_INTRCTRL_INT 0x04 /* INT_STATUS -and- MASTER_INT_EN */ 41*4882a593Smuzhiyun #define IOAT_INTRCTRL_MSIX_VECTOR_CONTROL 0x08 /* Enable all MSI-X vectors */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define IOAT_ATTNSTATUS_OFFSET 0x04 /* Each bit is a channel */ 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define IOAT_VER_OFFSET 0x08 /* 8-bit */ 46*4882a593Smuzhiyun #define IOAT_VER_MAJOR_MASK 0xF0 47*4882a593Smuzhiyun #define IOAT_VER_MINOR_MASK 0x0F 48*4882a593Smuzhiyun #define GET_IOAT_VER_MAJOR(x) (((x) & IOAT_VER_MAJOR_MASK) >> 4) 49*4882a593Smuzhiyun #define GET_IOAT_VER_MINOR(x) ((x) & IOAT_VER_MINOR_MASK) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define IOAT_PERPORTOFFSET_OFFSET 0x0A /* 16-bit */ 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define IOAT_INTRDELAY_OFFSET 0x0C /* 16-bit */ 54*4882a593Smuzhiyun #define IOAT_INTRDELAY_MASK 0x3FFF /* Interrupt Delay Time */ 55*4882a593Smuzhiyun #define IOAT_INTRDELAY_COALESE_SUPPORT 0x8000 /* Interrupt Coalescing Supported */ 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define IOAT_DEVICE_STATUS_OFFSET 0x0E /* 16-bit */ 58*4882a593Smuzhiyun #define IOAT_DEVICE_STATUS_DEGRADED_MODE 0x0001 59*4882a593Smuzhiyun #define IOAT_DEVICE_MMIO_RESTRICTED 0x0002 60*4882a593Smuzhiyun #define IOAT_DEVICE_MEMORY_BYPASS 0x0004 61*4882a593Smuzhiyun #define IOAT_DEVICE_ADDRESS_REMAPPING 0x0008 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define IOAT_DMA_CAP_OFFSET 0x10 /* 32-bit */ 64*4882a593Smuzhiyun #define IOAT_CAP_PAGE_BREAK 0x00000001 65*4882a593Smuzhiyun #define IOAT_CAP_CRC 0x00000002 66*4882a593Smuzhiyun #define IOAT_CAP_SKIP_MARKER 0x00000004 67*4882a593Smuzhiyun #define IOAT_CAP_DCA 0x00000010 68*4882a593Smuzhiyun #define IOAT_CAP_CRC_MOVE 0x00000020 69*4882a593Smuzhiyun #define IOAT_CAP_FILL_BLOCK 0x00000040 70*4882a593Smuzhiyun #define IOAT_CAP_APIC 0x00000080 71*4882a593Smuzhiyun #define IOAT_CAP_XOR 0x00000100 72*4882a593Smuzhiyun #define IOAT_CAP_PQ 0x00000200 73*4882a593Smuzhiyun #define IOAT_CAP_DWBES 0x00002000 74*4882a593Smuzhiyun #define IOAT_CAP_RAID16SS 0x00020000 75*4882a593Smuzhiyun #define IOAT_CAP_DPS 0x00800000 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define IOAT_PREFETCH_LIMIT_OFFSET 0x4C /* CHWPREFLMT */ 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #define IOAT_CHANNEL_MMIO_SIZE 0x80 /* Each Channel MMIO space is this size */ 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* DMA Channel Registers */ 82*4882a593Smuzhiyun #define IOAT_CHANCTRL_OFFSET 0x00 /* 16-bit Channel Control Register */ 83*4882a593Smuzhiyun #define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK 0xF000 84*4882a593Smuzhiyun #define IOAT3_CHANCTRL_COMPL_DCA_EN 0x0200 85*4882a593Smuzhiyun #define IOAT_CHANCTRL_CHANNEL_IN_USE 0x0100 86*4882a593Smuzhiyun #define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL 0x0020 87*4882a593Smuzhiyun #define IOAT_CHANCTRL_ERR_INT_EN 0x0010 88*4882a593Smuzhiyun #define IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008 89*4882a593Smuzhiyun #define IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004 90*4882a593Smuzhiyun #define IOAT_CHANCTRL_INT_REARM 0x0001 91*4882a593Smuzhiyun #define IOAT_CHANCTRL_RUN (IOAT_CHANCTRL_INT_REARM |\ 92*4882a593Smuzhiyun IOAT_CHANCTRL_ERR_INT_EN |\ 93*4882a593Smuzhiyun IOAT_CHANCTRL_ERR_COMPLETION_EN |\ 94*4882a593Smuzhiyun IOAT_CHANCTRL_ANY_ERR_ABORT_EN) 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #define IOAT_DMA_COMP_OFFSET 0x02 /* 16-bit DMA channel compatibility */ 97*4882a593Smuzhiyun #define IOAT_DMA_COMP_V1 0x0001 /* Compatibility with DMA version 1 */ 98*4882a593Smuzhiyun #define IOAT_DMA_COMP_V2 0x0002 /* Compatibility with DMA version 2 */ 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #define IOAT_CHANSTS_OFFSET 0x08 /* 64-bit Channel Status Register */ 101*4882a593Smuzhiyun #define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR (~0x3fULL) 102*4882a593Smuzhiyun #define IOAT_CHANSTS_SOFT_ERR 0x10ULL 103*4882a593Smuzhiyun #define IOAT_CHANSTS_UNAFFILIATED_ERR 0x8ULL 104*4882a593Smuzhiyun #define IOAT_CHANSTS_STATUS 0x7ULL 105*4882a593Smuzhiyun #define IOAT_CHANSTS_ACTIVE 0x0 106*4882a593Smuzhiyun #define IOAT_CHANSTS_DONE 0x1 107*4882a593Smuzhiyun #define IOAT_CHANSTS_SUSPENDED 0x2 108*4882a593Smuzhiyun #define IOAT_CHANSTS_HALTED 0x3 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #define IOAT_CHAN_DMACOUNT_OFFSET 0x06 /* 16-bit DMA Count register */ 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun #define IOAT_DCACTRL_OFFSET 0x30 /* 32 bit Direct Cache Access Control Register */ 115*4882a593Smuzhiyun #define IOAT_DCACTRL_CMPL_WRITE_ENABLE 0x10000 116*4882a593Smuzhiyun #define IOAT_DCACTRL_TARGET_CPU_MASK 0xFFFF /* APIC ID */ 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun /* CB DCA Memory Space Registers */ 119*4882a593Smuzhiyun #define IOAT_DCAOFFSET_OFFSET 0x14 120*4882a593Smuzhiyun /* CB_BAR + IOAT_DCAOFFSET value */ 121*4882a593Smuzhiyun #define IOAT_DCA_VER_OFFSET 0x00 122*4882a593Smuzhiyun #define IOAT_DCA_VER_MAJOR_MASK 0xF0 123*4882a593Smuzhiyun #define IOAT_DCA_VER_MINOR_MASK 0x0F 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun #define IOAT_DCA_COMP_OFFSET 0x02 126*4882a593Smuzhiyun #define IOAT_DCA_COMP_V1 0x1 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun #define IOAT_FSB_CAPABILITY_OFFSET 0x04 129*4882a593Smuzhiyun #define IOAT_FSB_CAPABILITY_PREFETCH 0x1 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun #define IOAT_PCI_CAPABILITY_OFFSET 0x06 132*4882a593Smuzhiyun #define IOAT_PCI_CAPABILITY_MEMWR 0x1 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #define IOAT_FSB_CAP_ENABLE_OFFSET 0x08 135*4882a593Smuzhiyun #define IOAT_FSB_CAP_ENABLE_PREFETCH 0x1 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun #define IOAT_PCI_CAP_ENABLE_OFFSET 0x0A 138*4882a593Smuzhiyun #define IOAT_PCI_CAP_ENABLE_MEMWR 0x1 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun #define IOAT_APICID_TAG_MAP_OFFSET 0x0C 141*4882a593Smuzhiyun #define IOAT_APICID_TAG_MAP_TAG0 0x0000000F 142*4882a593Smuzhiyun #define IOAT_APICID_TAG_MAP_TAG0_SHIFT 0 143*4882a593Smuzhiyun #define IOAT_APICID_TAG_MAP_TAG1 0x000000F0 144*4882a593Smuzhiyun #define IOAT_APICID_TAG_MAP_TAG1_SHIFT 4 145*4882a593Smuzhiyun #define IOAT_APICID_TAG_MAP_TAG2 0x00000F00 146*4882a593Smuzhiyun #define IOAT_APICID_TAG_MAP_TAG2_SHIFT 8 147*4882a593Smuzhiyun #define IOAT_APICID_TAG_MAP_TAG3 0x0000F000 148*4882a593Smuzhiyun #define IOAT_APICID_TAG_MAP_TAG3_SHIFT 12 149*4882a593Smuzhiyun #define IOAT_APICID_TAG_MAP_TAG4 0x000F0000 150*4882a593Smuzhiyun #define IOAT_APICID_TAG_MAP_TAG4_SHIFT 16 151*4882a593Smuzhiyun #define IOAT_APICID_TAG_CB2_VALID 0x8080808080 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun #define IOAT_DCA_GREQID_OFFSET 0x10 154*4882a593Smuzhiyun #define IOAT_DCA_GREQID_SIZE 0x04 155*4882a593Smuzhiyun #define IOAT_DCA_GREQID_MASK 0xFFFF 156*4882a593Smuzhiyun #define IOAT_DCA_GREQID_IGNOREFUN 0x10000000 157*4882a593Smuzhiyun #define IOAT_DCA_GREQID_VALID 0x20000000 158*4882a593Smuzhiyun #define IOAT_DCA_GREQID_LASTID 0x80000000 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun #define IOAT3_CSI_CAPABILITY_OFFSET 0x08 161*4882a593Smuzhiyun #define IOAT3_CSI_CAPABILITY_PREFETCH 0x1 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun #define IOAT3_PCI_CAPABILITY_OFFSET 0x0A 164*4882a593Smuzhiyun #define IOAT3_PCI_CAPABILITY_MEMWR 0x1 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun #define IOAT3_CSI_CONTROL_OFFSET 0x0C 167*4882a593Smuzhiyun #define IOAT3_CSI_CONTROL_PREFETCH 0x1 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun #define IOAT3_PCI_CONTROL_OFFSET 0x0E 170*4882a593Smuzhiyun #define IOAT3_PCI_CONTROL_MEMWR 0x1 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun #define IOAT3_APICID_TAG_MAP_OFFSET 0x10 173*4882a593Smuzhiyun #define IOAT3_APICID_TAG_MAP_OFFSET_LOW 0x10 174*4882a593Smuzhiyun #define IOAT3_APICID_TAG_MAP_OFFSET_HIGH 0x14 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun #define IOAT3_DCA_GREQID_OFFSET 0x02 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun #define IOAT1_CHAINADDR_OFFSET 0x0C /* 64-bit Descriptor Chain Address Register */ 179*4882a593Smuzhiyun #define IOAT2_CHAINADDR_OFFSET 0x10 /* 64-bit Descriptor Chain Address Register */ 180*4882a593Smuzhiyun #define IOAT_CHAINADDR_OFFSET(ver) ((ver) < IOAT_VER_2_0 \ 181*4882a593Smuzhiyun ? IOAT1_CHAINADDR_OFFSET : IOAT2_CHAINADDR_OFFSET) 182*4882a593Smuzhiyun #define IOAT1_CHAINADDR_OFFSET_LOW 0x0C 183*4882a593Smuzhiyun #define IOAT2_CHAINADDR_OFFSET_LOW 0x10 184*4882a593Smuzhiyun #define IOAT_CHAINADDR_OFFSET_LOW(ver) ((ver) < IOAT_VER_2_0 \ 185*4882a593Smuzhiyun ? IOAT1_CHAINADDR_OFFSET_LOW : IOAT2_CHAINADDR_OFFSET_LOW) 186*4882a593Smuzhiyun #define IOAT1_CHAINADDR_OFFSET_HIGH 0x10 187*4882a593Smuzhiyun #define IOAT2_CHAINADDR_OFFSET_HIGH 0x14 188*4882a593Smuzhiyun #define IOAT_CHAINADDR_OFFSET_HIGH(ver) ((ver) < IOAT_VER_2_0 \ 189*4882a593Smuzhiyun ? IOAT1_CHAINADDR_OFFSET_HIGH : IOAT2_CHAINADDR_OFFSET_HIGH) 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun #define IOAT1_CHANCMD_OFFSET 0x14 /* 8-bit DMA Channel Command Register */ 192*4882a593Smuzhiyun #define IOAT2_CHANCMD_OFFSET 0x04 /* 8-bit DMA Channel Command Register */ 193*4882a593Smuzhiyun #define IOAT_CHANCMD_OFFSET(ver) ((ver) < IOAT_VER_2_0 \ 194*4882a593Smuzhiyun ? IOAT1_CHANCMD_OFFSET : IOAT2_CHANCMD_OFFSET) 195*4882a593Smuzhiyun #define IOAT_CHANCMD_RESET 0x20 196*4882a593Smuzhiyun #define IOAT_CHANCMD_RESUME 0x10 197*4882a593Smuzhiyun #define IOAT_CHANCMD_ABORT 0x08 198*4882a593Smuzhiyun #define IOAT_CHANCMD_SUSPEND 0x04 199*4882a593Smuzhiyun #define IOAT_CHANCMD_APPEND 0x02 200*4882a593Smuzhiyun #define IOAT_CHANCMD_START 0x01 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun #define IOAT_CHANCMP_OFFSET 0x18 /* 64-bit Channel Completion Address Register */ 203*4882a593Smuzhiyun #define IOAT_CHANCMP_OFFSET_LOW 0x18 204*4882a593Smuzhiyun #define IOAT_CHANCMP_OFFSET_HIGH 0x1C 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun #define IOAT_CDAR_OFFSET 0x20 /* 64-bit Current Descriptor Address Register */ 207*4882a593Smuzhiyun #define IOAT_CDAR_OFFSET_LOW 0x20 208*4882a593Smuzhiyun #define IOAT_CDAR_OFFSET_HIGH 0x24 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun #define IOAT_CHANERR_OFFSET 0x28 /* 32-bit Channel Error Register */ 211*4882a593Smuzhiyun #define IOAT_CHANERR_SRC_ADDR_ERR 0x0001 212*4882a593Smuzhiyun #define IOAT_CHANERR_DEST_ADDR_ERR 0x0002 213*4882a593Smuzhiyun #define IOAT_CHANERR_NEXT_ADDR_ERR 0x0004 214*4882a593Smuzhiyun #define IOAT_CHANERR_NEXT_DESC_ALIGN_ERR 0x0008 215*4882a593Smuzhiyun #define IOAT_CHANERR_CHAIN_ADDR_VALUE_ERR 0x0010 216*4882a593Smuzhiyun #define IOAT_CHANERR_CHANCMD_ERR 0x0020 217*4882a593Smuzhiyun #define IOAT_CHANERR_CHIPSET_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0040 218*4882a593Smuzhiyun #define IOAT_CHANERR_DMA_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0080 219*4882a593Smuzhiyun #define IOAT_CHANERR_READ_DATA_ERR 0x0100 220*4882a593Smuzhiyun #define IOAT_CHANERR_WRITE_DATA_ERR 0x0200 221*4882a593Smuzhiyun #define IOAT_CHANERR_CONTROL_ERR 0x0400 222*4882a593Smuzhiyun #define IOAT_CHANERR_LENGTH_ERR 0x0800 223*4882a593Smuzhiyun #define IOAT_CHANERR_COMPLETION_ADDR_ERR 0x1000 224*4882a593Smuzhiyun #define IOAT_CHANERR_INT_CONFIGURATION_ERR 0x2000 225*4882a593Smuzhiyun #define IOAT_CHANERR_SOFT_ERR 0x4000 226*4882a593Smuzhiyun #define IOAT_CHANERR_UNAFFILIATED_ERR 0x8000 227*4882a593Smuzhiyun #define IOAT_CHANERR_XOR_P_OR_CRC_ERR 0x10000 228*4882a593Smuzhiyun #define IOAT_CHANERR_XOR_Q_ERR 0x20000 229*4882a593Smuzhiyun #define IOAT_CHANERR_DESCRIPTOR_COUNT_ERR 0x40000 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun #define IOAT_CHANERR_HANDLE_MASK (IOAT_CHANERR_XOR_P_OR_CRC_ERR | IOAT_CHANERR_XOR_Q_ERR) 232*4882a593Smuzhiyun #define IOAT_CHANERR_RECOVER_MASK (IOAT_CHANERR_READ_DATA_ERR | \ 233*4882a593Smuzhiyun IOAT_CHANERR_WRITE_DATA_ERR) 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun #define IOAT_CHANERR_MASK_OFFSET 0x2C /* 32-bit Channel Error Register */ 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun #define IOAT_CHAN_DRSCTL_OFFSET 0xB6 238*4882a593Smuzhiyun #define IOAT_CHAN_DRSZ_4KB 0x0000 239*4882a593Smuzhiyun #define IOAT_CHAN_DRSZ_8KB 0x0001 240*4882a593Smuzhiyun #define IOAT_CHAN_DRSZ_2MB 0x0009 241*4882a593Smuzhiyun #define IOAT_CHAN_DRS_EN 0x0100 242*4882a593Smuzhiyun #define IOAT_CHAN_DRS_AUTOWRAP 0x0200 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun #define IOAT_CHAN_LTR_SWSEL_OFFSET 0xBC 245*4882a593Smuzhiyun #define IOAT_CHAN_LTR_SWSEL_ACTIVE 0x0 246*4882a593Smuzhiyun #define IOAT_CHAN_LTR_SWSEL_IDLE 0x1 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun #define IOAT_CHAN_LTR_ACTIVE_OFFSET 0xC0 249*4882a593Smuzhiyun #define IOAT_CHAN_LTR_ACTIVE_SNVAL 0x0000 /* 0 us */ 250*4882a593Smuzhiyun #define IOAT_CHAN_LTR_ACTIVE_SNLATSCALE 0x0800 /* 1us scale */ 251*4882a593Smuzhiyun #define IOAT_CHAN_LTR_ACTIVE_SNREQMNT 0x8000 /* snoop req enable */ 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun #define IOAT_CHAN_LTR_IDLE_OFFSET 0xC4 254*4882a593Smuzhiyun #define IOAT_CHAN_LTR_IDLE_SNVAL 0x0258 /* 600 us */ 255*4882a593Smuzhiyun #define IOAT_CHAN_LTR_IDLE_SNLATSCALE 0x0800 /* 1us scale */ 256*4882a593Smuzhiyun #define IOAT_CHAN_LTR_IDLE_SNREQMNT 0x8000 /* snoop req enable */ 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun #endif /* _IOAT_REGISTERS_H_ */ 259