1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Intel I/OAT DMA Linux driver
4*4882a593Smuzhiyun * Copyright(c) 2007 - 2009 Intel Corporation.
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/kernel.h>
8*4882a593Smuzhiyun #include <linux/pci.h>
9*4882a593Smuzhiyun #include <linux/smp.h>
10*4882a593Smuzhiyun #include <linux/interrupt.h>
11*4882a593Smuzhiyun #include <linux/dca.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun /* either a kernel change is needed, or we need something like this in kernel */
14*4882a593Smuzhiyun #ifndef CONFIG_SMP
15*4882a593Smuzhiyun #include <asm/smp.h>
16*4882a593Smuzhiyun #undef cpu_physical_id
17*4882a593Smuzhiyun #define cpu_physical_id(cpu) (cpuid_ebx(1) >> 24)
18*4882a593Smuzhiyun #endif
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include "dma.h"
21*4882a593Smuzhiyun #include "registers.h"
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /*
24*4882a593Smuzhiyun * Bit 7 of a tag map entry is the "valid" bit, if it is set then bits 0:6
25*4882a593Smuzhiyun * contain the bit number of the APIC ID to map into the DCA tag. If the valid
26*4882a593Smuzhiyun * bit is not set, then the value must be 0 or 1 and defines the bit in the tag.
27*4882a593Smuzhiyun */
28*4882a593Smuzhiyun #define DCA_TAG_MAP_VALID 0x80
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #define DCA3_TAG_MAP_BIT_TO_INV 0x80
31*4882a593Smuzhiyun #define DCA3_TAG_MAP_BIT_TO_SEL 0x40
32*4882a593Smuzhiyun #define DCA3_TAG_MAP_LITERAL_VAL 0x1
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #define DCA_TAG_MAP_MASK 0xDF
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* expected tag map bytes for I/OAT ver.2 */
37*4882a593Smuzhiyun #define DCA2_TAG_MAP_BYTE0 0x80
38*4882a593Smuzhiyun #define DCA2_TAG_MAP_BYTE1 0x0
39*4882a593Smuzhiyun #define DCA2_TAG_MAP_BYTE2 0x81
40*4882a593Smuzhiyun #define DCA2_TAG_MAP_BYTE3 0x82
41*4882a593Smuzhiyun #define DCA2_TAG_MAP_BYTE4 0x82
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /*
44*4882a593Smuzhiyun * "Legacy" DCA systems do not implement the DCA register set in the
45*4882a593Smuzhiyun * I/OAT device. Software needs direct support for their tag mappings.
46*4882a593Smuzhiyun */
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun #define APICID_BIT(x) (DCA_TAG_MAP_VALID | (x))
49*4882a593Smuzhiyun #define IOAT_TAG_MAP_LEN 8
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /* pack PCI B/D/F into a u16 */
dcaid_from_pcidev(struct pci_dev * pci)52*4882a593Smuzhiyun static inline u16 dcaid_from_pcidev(struct pci_dev *pci)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun return (pci->bus->number << 8) | pci->devfn;
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
dca_enabled_in_bios(struct pci_dev * pdev)57*4882a593Smuzhiyun static int dca_enabled_in_bios(struct pci_dev *pdev)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun /* CPUID level 9 returns DCA configuration */
60*4882a593Smuzhiyun /* Bit 0 indicates DCA enabled by the BIOS */
61*4882a593Smuzhiyun unsigned long cpuid_level_9;
62*4882a593Smuzhiyun int res;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun cpuid_level_9 = cpuid_eax(9);
65*4882a593Smuzhiyun res = test_bit(0, &cpuid_level_9);
66*4882a593Smuzhiyun if (!res)
67*4882a593Smuzhiyun dev_dbg(&pdev->dev, "DCA is disabled in BIOS\n");
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun return res;
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
system_has_dca_enabled(struct pci_dev * pdev)72*4882a593Smuzhiyun int system_has_dca_enabled(struct pci_dev *pdev)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun if (boot_cpu_has(X86_FEATURE_DCA))
75*4882a593Smuzhiyun return dca_enabled_in_bios(pdev);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun dev_dbg(&pdev->dev, "boot cpu doesn't have X86_FEATURE_DCA\n");
78*4882a593Smuzhiyun return 0;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun struct ioat_dca_slot {
82*4882a593Smuzhiyun struct pci_dev *pdev; /* requester device */
83*4882a593Smuzhiyun u16 rid; /* requester id, as used by IOAT */
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun #define IOAT_DCA_MAX_REQ 6
87*4882a593Smuzhiyun #define IOAT3_DCA_MAX_REQ 2
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun struct ioat_dca_priv {
90*4882a593Smuzhiyun void __iomem *iobase;
91*4882a593Smuzhiyun void __iomem *dca_base;
92*4882a593Smuzhiyun int max_requesters;
93*4882a593Smuzhiyun int requester_count;
94*4882a593Smuzhiyun u8 tag_map[IOAT_TAG_MAP_LEN];
95*4882a593Smuzhiyun struct ioat_dca_slot req_slots[];
96*4882a593Smuzhiyun };
97*4882a593Smuzhiyun
ioat_dca_dev_managed(struct dca_provider * dca,struct device * dev)98*4882a593Smuzhiyun static int ioat_dca_dev_managed(struct dca_provider *dca,
99*4882a593Smuzhiyun struct device *dev)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun struct ioat_dca_priv *ioatdca = dca_priv(dca);
102*4882a593Smuzhiyun struct pci_dev *pdev;
103*4882a593Smuzhiyun int i;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun pdev = to_pci_dev(dev);
106*4882a593Smuzhiyun for (i = 0; i < ioatdca->max_requesters; i++) {
107*4882a593Smuzhiyun if (ioatdca->req_slots[i].pdev == pdev)
108*4882a593Smuzhiyun return 1;
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun return 0;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
ioat_dca_add_requester(struct dca_provider * dca,struct device * dev)113*4882a593Smuzhiyun static int ioat_dca_add_requester(struct dca_provider *dca, struct device *dev)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun struct ioat_dca_priv *ioatdca = dca_priv(dca);
116*4882a593Smuzhiyun struct pci_dev *pdev;
117*4882a593Smuzhiyun int i;
118*4882a593Smuzhiyun u16 id;
119*4882a593Smuzhiyun u16 global_req_table;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun /* This implementation only supports PCI-Express */
122*4882a593Smuzhiyun if (!dev_is_pci(dev))
123*4882a593Smuzhiyun return -ENODEV;
124*4882a593Smuzhiyun pdev = to_pci_dev(dev);
125*4882a593Smuzhiyun id = dcaid_from_pcidev(pdev);
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun if (ioatdca->requester_count == ioatdca->max_requesters)
128*4882a593Smuzhiyun return -ENODEV;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun for (i = 0; i < ioatdca->max_requesters; i++) {
131*4882a593Smuzhiyun if (ioatdca->req_slots[i].pdev == NULL) {
132*4882a593Smuzhiyun /* found an empty slot */
133*4882a593Smuzhiyun ioatdca->requester_count++;
134*4882a593Smuzhiyun ioatdca->req_slots[i].pdev = pdev;
135*4882a593Smuzhiyun ioatdca->req_slots[i].rid = id;
136*4882a593Smuzhiyun global_req_table =
137*4882a593Smuzhiyun readw(ioatdca->dca_base + IOAT3_DCA_GREQID_OFFSET);
138*4882a593Smuzhiyun writel(id | IOAT_DCA_GREQID_VALID,
139*4882a593Smuzhiyun ioatdca->iobase + global_req_table + (i * 4));
140*4882a593Smuzhiyun return i;
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun /* Error, ioatdma->requester_count is out of whack */
144*4882a593Smuzhiyun return -EFAULT;
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun
ioat_dca_remove_requester(struct dca_provider * dca,struct device * dev)147*4882a593Smuzhiyun static int ioat_dca_remove_requester(struct dca_provider *dca,
148*4882a593Smuzhiyun struct device *dev)
149*4882a593Smuzhiyun {
150*4882a593Smuzhiyun struct ioat_dca_priv *ioatdca = dca_priv(dca);
151*4882a593Smuzhiyun struct pci_dev *pdev;
152*4882a593Smuzhiyun int i;
153*4882a593Smuzhiyun u16 global_req_table;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun /* This implementation only supports PCI-Express */
156*4882a593Smuzhiyun if (!dev_is_pci(dev))
157*4882a593Smuzhiyun return -ENODEV;
158*4882a593Smuzhiyun pdev = to_pci_dev(dev);
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun for (i = 0; i < ioatdca->max_requesters; i++) {
161*4882a593Smuzhiyun if (ioatdca->req_slots[i].pdev == pdev) {
162*4882a593Smuzhiyun global_req_table =
163*4882a593Smuzhiyun readw(ioatdca->dca_base + IOAT3_DCA_GREQID_OFFSET);
164*4882a593Smuzhiyun writel(0, ioatdca->iobase + global_req_table + (i * 4));
165*4882a593Smuzhiyun ioatdca->req_slots[i].pdev = NULL;
166*4882a593Smuzhiyun ioatdca->req_slots[i].rid = 0;
167*4882a593Smuzhiyun ioatdca->requester_count--;
168*4882a593Smuzhiyun return i;
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun return -ENODEV;
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun
ioat_dca_get_tag(struct dca_provider * dca,struct device * dev,int cpu)174*4882a593Smuzhiyun static u8 ioat_dca_get_tag(struct dca_provider *dca,
175*4882a593Smuzhiyun struct device *dev,
176*4882a593Smuzhiyun int cpu)
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun u8 tag;
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun struct ioat_dca_priv *ioatdca = dca_priv(dca);
181*4882a593Smuzhiyun int i, apic_id, bit, value;
182*4882a593Smuzhiyun u8 entry;
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun tag = 0;
185*4882a593Smuzhiyun apic_id = cpu_physical_id(cpu);
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun for (i = 0; i < IOAT_TAG_MAP_LEN; i++) {
188*4882a593Smuzhiyun entry = ioatdca->tag_map[i];
189*4882a593Smuzhiyun if (entry & DCA3_TAG_MAP_BIT_TO_SEL) {
190*4882a593Smuzhiyun bit = entry &
191*4882a593Smuzhiyun ~(DCA3_TAG_MAP_BIT_TO_SEL | DCA3_TAG_MAP_BIT_TO_INV);
192*4882a593Smuzhiyun value = (apic_id & (1 << bit)) ? 1 : 0;
193*4882a593Smuzhiyun } else if (entry & DCA3_TAG_MAP_BIT_TO_INV) {
194*4882a593Smuzhiyun bit = entry & ~DCA3_TAG_MAP_BIT_TO_INV;
195*4882a593Smuzhiyun value = (apic_id & (1 << bit)) ? 0 : 1;
196*4882a593Smuzhiyun } else {
197*4882a593Smuzhiyun value = (entry & DCA3_TAG_MAP_LITERAL_VAL) ? 1 : 0;
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun tag |= (value << i);
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun return tag;
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun static const struct dca_ops ioat_dca_ops = {
206*4882a593Smuzhiyun .add_requester = ioat_dca_add_requester,
207*4882a593Smuzhiyun .remove_requester = ioat_dca_remove_requester,
208*4882a593Smuzhiyun .get_tag = ioat_dca_get_tag,
209*4882a593Smuzhiyun .dev_managed = ioat_dca_dev_managed,
210*4882a593Smuzhiyun };
211*4882a593Smuzhiyun
ioat_dca_count_dca_slots(void * iobase,u16 dca_offset)212*4882a593Smuzhiyun static int ioat_dca_count_dca_slots(void *iobase, u16 dca_offset)
213*4882a593Smuzhiyun {
214*4882a593Smuzhiyun int slots = 0;
215*4882a593Smuzhiyun u32 req;
216*4882a593Smuzhiyun u16 global_req_table;
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun global_req_table = readw(iobase + dca_offset + IOAT3_DCA_GREQID_OFFSET);
219*4882a593Smuzhiyun if (global_req_table == 0)
220*4882a593Smuzhiyun return 0;
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun do {
223*4882a593Smuzhiyun req = readl(iobase + global_req_table + (slots * sizeof(u32)));
224*4882a593Smuzhiyun slots++;
225*4882a593Smuzhiyun } while ((req & IOAT_DCA_GREQID_LASTID) == 0);
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun return slots;
228*4882a593Smuzhiyun }
229*4882a593Smuzhiyun
dca3_tag_map_invalid(u8 * tag_map)230*4882a593Smuzhiyun static inline int dca3_tag_map_invalid(u8 *tag_map)
231*4882a593Smuzhiyun {
232*4882a593Smuzhiyun /*
233*4882a593Smuzhiyun * If the tag map is not programmed by the BIOS the default is:
234*4882a593Smuzhiyun * 0x80 0x80 0x80 0x80 0x80 0x00 0x00 0x00
235*4882a593Smuzhiyun *
236*4882a593Smuzhiyun * This an invalid map and will result in only 2 possible tags
237*4882a593Smuzhiyun * 0x1F and 0x00. 0x00 is an invalid DCA tag so we know that
238*4882a593Smuzhiyun * this entire definition is invalid.
239*4882a593Smuzhiyun */
240*4882a593Smuzhiyun return ((tag_map[0] == DCA_TAG_MAP_VALID) &&
241*4882a593Smuzhiyun (tag_map[1] == DCA_TAG_MAP_VALID) &&
242*4882a593Smuzhiyun (tag_map[2] == DCA_TAG_MAP_VALID) &&
243*4882a593Smuzhiyun (tag_map[3] == DCA_TAG_MAP_VALID) &&
244*4882a593Smuzhiyun (tag_map[4] == DCA_TAG_MAP_VALID));
245*4882a593Smuzhiyun }
246*4882a593Smuzhiyun
ioat_dca_init(struct pci_dev * pdev,void __iomem * iobase)247*4882a593Smuzhiyun struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase)
248*4882a593Smuzhiyun {
249*4882a593Smuzhiyun struct dca_provider *dca;
250*4882a593Smuzhiyun struct ioat_dca_priv *ioatdca;
251*4882a593Smuzhiyun int slots;
252*4882a593Smuzhiyun int i;
253*4882a593Smuzhiyun int err;
254*4882a593Smuzhiyun u16 dca_offset;
255*4882a593Smuzhiyun u16 csi_fsb_control;
256*4882a593Smuzhiyun u16 pcie_control;
257*4882a593Smuzhiyun u8 bit;
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun union {
260*4882a593Smuzhiyun u64 full;
261*4882a593Smuzhiyun struct {
262*4882a593Smuzhiyun u32 low;
263*4882a593Smuzhiyun u32 high;
264*4882a593Smuzhiyun };
265*4882a593Smuzhiyun } tag_map;
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun if (!system_has_dca_enabled(pdev))
268*4882a593Smuzhiyun return NULL;
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun dca_offset = readw(iobase + IOAT_DCAOFFSET_OFFSET);
271*4882a593Smuzhiyun if (dca_offset == 0)
272*4882a593Smuzhiyun return NULL;
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun slots = ioat_dca_count_dca_slots(iobase, dca_offset);
275*4882a593Smuzhiyun if (slots == 0)
276*4882a593Smuzhiyun return NULL;
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun dca = alloc_dca_provider(&ioat_dca_ops,
279*4882a593Smuzhiyun struct_size(ioatdca, req_slots, slots));
280*4882a593Smuzhiyun if (!dca)
281*4882a593Smuzhiyun return NULL;
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun ioatdca = dca_priv(dca);
284*4882a593Smuzhiyun ioatdca->iobase = iobase;
285*4882a593Smuzhiyun ioatdca->dca_base = iobase + dca_offset;
286*4882a593Smuzhiyun ioatdca->max_requesters = slots;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun /* some bios might not know to turn these on */
289*4882a593Smuzhiyun csi_fsb_control = readw(ioatdca->dca_base + IOAT3_CSI_CONTROL_OFFSET);
290*4882a593Smuzhiyun if ((csi_fsb_control & IOAT3_CSI_CONTROL_PREFETCH) == 0) {
291*4882a593Smuzhiyun csi_fsb_control |= IOAT3_CSI_CONTROL_PREFETCH;
292*4882a593Smuzhiyun writew(csi_fsb_control,
293*4882a593Smuzhiyun ioatdca->dca_base + IOAT3_CSI_CONTROL_OFFSET);
294*4882a593Smuzhiyun }
295*4882a593Smuzhiyun pcie_control = readw(ioatdca->dca_base + IOAT3_PCI_CONTROL_OFFSET);
296*4882a593Smuzhiyun if ((pcie_control & IOAT3_PCI_CONTROL_MEMWR) == 0) {
297*4882a593Smuzhiyun pcie_control |= IOAT3_PCI_CONTROL_MEMWR;
298*4882a593Smuzhiyun writew(pcie_control,
299*4882a593Smuzhiyun ioatdca->dca_base + IOAT3_PCI_CONTROL_OFFSET);
300*4882a593Smuzhiyun }
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun /* TODO version, compatibility and configuration checks */
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun /* copy out the APIC to DCA tag map */
306*4882a593Smuzhiyun tag_map.low =
307*4882a593Smuzhiyun readl(ioatdca->dca_base + IOAT3_APICID_TAG_MAP_OFFSET_LOW);
308*4882a593Smuzhiyun tag_map.high =
309*4882a593Smuzhiyun readl(ioatdca->dca_base + IOAT3_APICID_TAG_MAP_OFFSET_HIGH);
310*4882a593Smuzhiyun for (i = 0; i < 8; i++) {
311*4882a593Smuzhiyun bit = tag_map.full >> (8 * i);
312*4882a593Smuzhiyun ioatdca->tag_map[i] = bit & DCA_TAG_MAP_MASK;
313*4882a593Smuzhiyun }
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun if (dca3_tag_map_invalid(ioatdca->tag_map)) {
316*4882a593Smuzhiyun add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
317*4882a593Smuzhiyun pr_warn_once("%s %s: APICID_TAG_MAP set incorrectly by BIOS, disabling DCA\n",
318*4882a593Smuzhiyun dev_driver_string(&pdev->dev),
319*4882a593Smuzhiyun dev_name(&pdev->dev));
320*4882a593Smuzhiyun free_dca_provider(dca);
321*4882a593Smuzhiyun return NULL;
322*4882a593Smuzhiyun }
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun err = register_dca_provider(dca, &pdev->dev);
325*4882a593Smuzhiyun if (err) {
326*4882a593Smuzhiyun free_dca_provider(dca);
327*4882a593Smuzhiyun return NULL;
328*4882a593Smuzhiyun }
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun return dca;
331*4882a593Smuzhiyun }
332