1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Driver for the High Speed UART DMA
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2015 Intel Corporation
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Partially based on the bits found in drivers/tty/serial/mfd.c.
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #ifndef __DMA_HSU_H__
11*4882a593Smuzhiyun #define __DMA_HSU_H__
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/spinlock.h>
14*4882a593Smuzhiyun #include <linux/dma/hsu.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include "../virt-dma.h"
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define HSU_CH_SR 0x00 /* channel status */
19*4882a593Smuzhiyun #define HSU_CH_CR 0x04 /* channel control */
20*4882a593Smuzhiyun #define HSU_CH_DCR 0x08 /* descriptor control */
21*4882a593Smuzhiyun #define HSU_CH_BSR 0x10 /* FIFO buffer size */
22*4882a593Smuzhiyun #define HSU_CH_MTSR 0x14 /* minimum transfer size */
23*4882a593Smuzhiyun #define HSU_CH_DxSAR(x) (0x20 + 8 * (x)) /* desc start addr */
24*4882a593Smuzhiyun #define HSU_CH_DxTSR(x) (0x24 + 8 * (x)) /* desc transfer size */
25*4882a593Smuzhiyun #define HSU_CH_D0SAR 0x20 /* desc 0 start addr */
26*4882a593Smuzhiyun #define HSU_CH_D0TSR 0x24 /* desc 0 transfer size */
27*4882a593Smuzhiyun #define HSU_CH_D1SAR 0x28
28*4882a593Smuzhiyun #define HSU_CH_D1TSR 0x2c
29*4882a593Smuzhiyun #define HSU_CH_D2SAR 0x30
30*4882a593Smuzhiyun #define HSU_CH_D2TSR 0x34
31*4882a593Smuzhiyun #define HSU_CH_D3SAR 0x38
32*4882a593Smuzhiyun #define HSU_CH_D3TSR 0x3c
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #define HSU_DMA_CHAN_NR_DESC 4
35*4882a593Smuzhiyun #define HSU_DMA_CHAN_LENGTH 0x40
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* Bits in HSU_CH_SR */
38*4882a593Smuzhiyun #define HSU_CH_SR_DESCTO(x) BIT(8 + (x))
39*4882a593Smuzhiyun #define HSU_CH_SR_DESCTO_ANY (BIT(11) | BIT(10) | BIT(9) | BIT(8))
40*4882a593Smuzhiyun #define HSU_CH_SR_CHE BIT(15)
41*4882a593Smuzhiyun #define HSU_CH_SR_DESCE(x) BIT(16 + (x))
42*4882a593Smuzhiyun #define HSU_CH_SR_DESCE_ANY (BIT(19) | BIT(18) | BIT(17) | BIT(16))
43*4882a593Smuzhiyun #define HSU_CH_SR_CDESC_ANY (BIT(31) | BIT(30))
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun /* Bits in HSU_CH_CR */
46*4882a593Smuzhiyun #define HSU_CH_CR_CHA BIT(0)
47*4882a593Smuzhiyun #define HSU_CH_CR_CHD BIT(1)
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* Bits in HSU_CH_DCR */
50*4882a593Smuzhiyun #define HSU_CH_DCR_DESCA(x) BIT(0 + (x))
51*4882a593Smuzhiyun #define HSU_CH_DCR_CHSOD(x) BIT(8 + (x))
52*4882a593Smuzhiyun #define HSU_CH_DCR_CHSOTO BIT(14)
53*4882a593Smuzhiyun #define HSU_CH_DCR_CHSOE BIT(15)
54*4882a593Smuzhiyun #define HSU_CH_DCR_CHDI(x) BIT(16 + (x))
55*4882a593Smuzhiyun #define HSU_CH_DCR_CHEI BIT(23)
56*4882a593Smuzhiyun #define HSU_CH_DCR_CHTOI(x) BIT(24 + (x))
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /* Bits in HSU_CH_DxTSR */
59*4882a593Smuzhiyun #define HSU_CH_DxTSR_MASK GENMASK(15, 0)
60*4882a593Smuzhiyun #define HSU_CH_DxTSR_TSR(x) ((x) & HSU_CH_DxTSR_MASK)
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun struct hsu_dma_sg {
63*4882a593Smuzhiyun dma_addr_t addr;
64*4882a593Smuzhiyun unsigned int len;
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun struct hsu_dma_desc {
68*4882a593Smuzhiyun struct virt_dma_desc vdesc;
69*4882a593Smuzhiyun enum dma_transfer_direction direction;
70*4882a593Smuzhiyun struct hsu_dma_sg *sg;
71*4882a593Smuzhiyun unsigned int nents;
72*4882a593Smuzhiyun size_t length;
73*4882a593Smuzhiyun unsigned int active;
74*4882a593Smuzhiyun enum dma_status status;
75*4882a593Smuzhiyun };
76*4882a593Smuzhiyun
to_hsu_dma_desc(struct virt_dma_desc * vdesc)77*4882a593Smuzhiyun static inline struct hsu_dma_desc *to_hsu_dma_desc(struct virt_dma_desc *vdesc)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun return container_of(vdesc, struct hsu_dma_desc, vdesc);
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun struct hsu_dma_chan {
83*4882a593Smuzhiyun struct virt_dma_chan vchan;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun void __iomem *reg;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /* hardware configuration */
88*4882a593Smuzhiyun enum dma_transfer_direction direction;
89*4882a593Smuzhiyun struct dma_slave_config config;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun struct hsu_dma_desc *desc;
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun
to_hsu_dma_chan(struct dma_chan * chan)94*4882a593Smuzhiyun static inline struct hsu_dma_chan *to_hsu_dma_chan(struct dma_chan *chan)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun return container_of(chan, struct hsu_dma_chan, vchan.chan);
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
hsu_chan_readl(struct hsu_dma_chan * hsuc,int offset)99*4882a593Smuzhiyun static inline u32 hsu_chan_readl(struct hsu_dma_chan *hsuc, int offset)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun return readl(hsuc->reg + offset);
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
hsu_chan_writel(struct hsu_dma_chan * hsuc,int offset,u32 value)104*4882a593Smuzhiyun static inline void hsu_chan_writel(struct hsu_dma_chan *hsuc, int offset,
105*4882a593Smuzhiyun u32 value)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun writel(value, hsuc->reg + offset);
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun struct hsu_dma {
111*4882a593Smuzhiyun struct dma_device dma;
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun /* channels */
114*4882a593Smuzhiyun struct hsu_dma_chan *chan;
115*4882a593Smuzhiyun unsigned short nr_channels;
116*4882a593Smuzhiyun };
117*4882a593Smuzhiyun
to_hsu_dma(struct dma_device * ddev)118*4882a593Smuzhiyun static inline struct hsu_dma *to_hsu_dma(struct dma_device *ddev)
119*4882a593Smuzhiyun {
120*4882a593Smuzhiyun return container_of(ddev, struct hsu_dma, dma);
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun #endif /* __DMA_HSU_H__ */
124