1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright 2019 NXP */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef __DPAA2_QDMA_H 5*4882a593Smuzhiyun #define __DPAA2_QDMA_H 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #define DPAA2_QDMA_STORE_SIZE 16 8*4882a593Smuzhiyun #define NUM_CH 8 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun struct dpaa2_qdma_sd_d { 11*4882a593Smuzhiyun u32 rsv:32; 12*4882a593Smuzhiyun union { 13*4882a593Smuzhiyun struct { 14*4882a593Smuzhiyun u32 ssd:12; /* souce stride distance */ 15*4882a593Smuzhiyun u32 sss:12; /* souce stride size */ 16*4882a593Smuzhiyun u32 rsv1:8; 17*4882a593Smuzhiyun } sdf; 18*4882a593Smuzhiyun struct { 19*4882a593Smuzhiyun u32 dsd:12; /* Destination stride distance */ 20*4882a593Smuzhiyun u32 dss:12; /* Destination stride size */ 21*4882a593Smuzhiyun u32 rsv2:8; 22*4882a593Smuzhiyun } ddf; 23*4882a593Smuzhiyun } df; 24*4882a593Smuzhiyun u32 rbpcmd; /* Route-by-port command */ 25*4882a593Smuzhiyun u32 cmd; 26*4882a593Smuzhiyun } __attribute__((__packed__)); 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* Source descriptor command read transaction type for RBP=0: */ 29*4882a593Smuzhiyun /* coherent copy of cacheable memory */ 30*4882a593Smuzhiyun #define QDMA_SD_CMD_RDTTYPE_COHERENT (0xb << 28) 31*4882a593Smuzhiyun /* Destination descriptor command write transaction type for RBP=0: */ 32*4882a593Smuzhiyun /* coherent copy of cacheable memory */ 33*4882a593Smuzhiyun #define QDMA_DD_CMD_WRTTYPE_COHERENT (0x6 << 28) 34*4882a593Smuzhiyun #define LX2160_QDMA_DD_CMD_WRTTYPE_COHERENT (0xb << 28) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define QMAN_FD_FMT_ENABLE BIT(0) /* frame list table enable */ 37*4882a593Smuzhiyun #define QMAN_FD_BMT_ENABLE BIT(15) /* bypass memory translation */ 38*4882a593Smuzhiyun #define QMAN_FD_BMT_DISABLE (0) /* bypass memory translation */ 39*4882a593Smuzhiyun #define QMAN_FD_SL_DISABLE (0) /* short lengthe disabled */ 40*4882a593Smuzhiyun #define QMAN_FD_SL_ENABLE BIT(14) /* short lengthe enabled */ 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define QDMA_FINAL_BIT_DISABLE (0) /* final bit disable */ 43*4882a593Smuzhiyun #define QDMA_FINAL_BIT_ENABLE BIT(31) /* final bit enable */ 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define QDMA_FD_SHORT_FORMAT BIT(11) /* short format */ 46*4882a593Smuzhiyun #define QDMA_FD_LONG_FORMAT (0) /* long format */ 47*4882a593Smuzhiyun #define QDMA_SER_DISABLE (8) /* no notification */ 48*4882a593Smuzhiyun #define QDMA_SER_CTX BIT(8) /* notification by FQD_CTX[fqid] */ 49*4882a593Smuzhiyun #define QDMA_SER_DEST (2 << 8) /* notification by destination desc */ 50*4882a593Smuzhiyun #define QDMA_SER_BOTH (3 << 8) /* soruce and dest notification */ 51*4882a593Smuzhiyun #define QDMA_FD_SPF_ENALBE BIT(30) /* source prefetch enable */ 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define QMAN_FD_VA_ENABLE BIT(14) /* Address used is virtual address */ 54*4882a593Smuzhiyun #define QMAN_FD_VA_DISABLE (0)/* Address used is a real address */ 55*4882a593Smuzhiyun /* Flow Context: 49bit physical address */ 56*4882a593Smuzhiyun #define QMAN_FD_CBMT_ENABLE BIT(15) 57*4882a593Smuzhiyun #define QMAN_FD_CBMT_DISABLE (0) /* Flow Context: 64bit virtual address */ 58*4882a593Smuzhiyun #define QMAN_FD_SC_DISABLE (0) /* stashing control */ 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define QDMA_FL_FMT_SBF (0x0) /* Single buffer frame */ 61*4882a593Smuzhiyun #define QDMA_FL_FMT_SGE (0x2) /* Scatter gather frame */ 62*4882a593Smuzhiyun #define QDMA_FL_BMT_ENABLE BIT(15) /* enable bypass memory translation */ 63*4882a593Smuzhiyun #define QDMA_FL_BMT_DISABLE (0x0) /* enable bypass memory translation */ 64*4882a593Smuzhiyun #define QDMA_FL_SL_LONG (0x0)/* long length */ 65*4882a593Smuzhiyun #define QDMA_FL_SL_SHORT (0x1) /* short length */ 66*4882a593Smuzhiyun #define QDMA_FL_F (0x1)/* last frame list bit */ 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /*Description of Frame list table structure*/ 69*4882a593Smuzhiyun struct dpaa2_qdma_chan { 70*4882a593Smuzhiyun struct dpaa2_qdma_engine *qdma; 71*4882a593Smuzhiyun struct virt_dma_chan vchan; 72*4882a593Smuzhiyun struct virt_dma_desc vdesc; 73*4882a593Smuzhiyun enum dma_status status; 74*4882a593Smuzhiyun u32 fqid; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* spinlock used by dpaa2 qdma driver */ 77*4882a593Smuzhiyun spinlock_t queue_lock; 78*4882a593Smuzhiyun struct dma_pool *fd_pool; 79*4882a593Smuzhiyun struct dma_pool *fl_pool; 80*4882a593Smuzhiyun struct dma_pool *sdd_pool; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun struct list_head comp_used; 83*4882a593Smuzhiyun struct list_head comp_free; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun struct dpaa2_qdma_comp { 88*4882a593Smuzhiyun dma_addr_t fd_bus_addr; 89*4882a593Smuzhiyun dma_addr_t fl_bus_addr; 90*4882a593Smuzhiyun dma_addr_t desc_bus_addr; 91*4882a593Smuzhiyun struct dpaa2_fd *fd_virt_addr; 92*4882a593Smuzhiyun struct dpaa2_fl_entry *fl_virt_addr; 93*4882a593Smuzhiyun struct dpaa2_qdma_sd_d *desc_virt_addr; 94*4882a593Smuzhiyun struct dpaa2_qdma_chan *qchan; 95*4882a593Smuzhiyun struct virt_dma_desc vdesc; 96*4882a593Smuzhiyun struct list_head list; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun struct dpaa2_qdma_engine { 100*4882a593Smuzhiyun struct dma_device dma_dev; 101*4882a593Smuzhiyun u32 n_chans; 102*4882a593Smuzhiyun struct dpaa2_qdma_chan chans[NUM_CH]; 103*4882a593Smuzhiyun int qdma_wrtype_fixup; 104*4882a593Smuzhiyun int desc_allocated; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun struct dpaa2_qdma_priv *priv; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun /* 110*4882a593Smuzhiyun * dpaa2_qdma_priv - driver private data 111*4882a593Smuzhiyun */ 112*4882a593Smuzhiyun struct dpaa2_qdma_priv { 113*4882a593Smuzhiyun int dpqdma_id; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun struct iommu_domain *iommu_domain; 116*4882a593Smuzhiyun struct dpdmai_attr dpdmai_attr; 117*4882a593Smuzhiyun struct device *dev; 118*4882a593Smuzhiyun struct fsl_mc_io *mc_io; 119*4882a593Smuzhiyun struct fsl_mc_device *dpdmai_dev; 120*4882a593Smuzhiyun u8 num_pairs; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun struct dpaa2_qdma_engine *dpaa2_qdma; 123*4882a593Smuzhiyun struct dpaa2_qdma_priv_per_prio *ppriv; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun struct dpdmai_rx_queue_attr rx_queue_attr[DPDMAI_PRIO_NUM]; 126*4882a593Smuzhiyun u32 tx_fqid[DPDMAI_PRIO_NUM]; 127*4882a593Smuzhiyun }; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun struct dpaa2_qdma_priv_per_prio { 130*4882a593Smuzhiyun int req_fqid; 131*4882a593Smuzhiyun int rsp_fqid; 132*4882a593Smuzhiyun int prio; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun struct dpaa2_io_store *store; 135*4882a593Smuzhiyun struct dpaa2_io_notification_ctx nctx; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun struct dpaa2_qdma_priv *priv; 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun static struct soc_device_attribute soc_fixup_tuning[] = { 141*4882a593Smuzhiyun { .family = "QorIQ LX2160A"}, 142*4882a593Smuzhiyun { }, 143*4882a593Smuzhiyun }; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun /* FD pool size: one FD + 3 Frame list + 2 source/destination descriptor */ 146*4882a593Smuzhiyun #define FD_POOL_SIZE (sizeof(struct dpaa2_fd) + \ 147*4882a593Smuzhiyun sizeof(struct dpaa2_fl_entry) * 3 + \ 148*4882a593Smuzhiyun sizeof(struct dpaa2_qdma_sd_d) * 2) 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun static void dpaa2_dpdmai_free_channels(struct dpaa2_qdma_engine *dpaa2_qdma); 151*4882a593Smuzhiyun static void dpaa2_dpdmai_free_comp(struct dpaa2_qdma_chan *qchan, 152*4882a593Smuzhiyun struct list_head *head); 153*4882a593Smuzhiyun #endif /* __DPAA2_QDMA_H */ 154