1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Driver for the Synopsys DesignWare DMA Controller
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2013 Intel Corporation
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #ifndef _DMA_DW_INTERNAL_H
9*4882a593Smuzhiyun #define _DMA_DW_INTERNAL_H
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/dma/dw.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include "regs.h"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun int do_dma_probe(struct dw_dma_chip *chip);
16*4882a593Smuzhiyun int do_dma_remove(struct dw_dma_chip *chip);
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun void do_dw_dma_on(struct dw_dma *dw);
19*4882a593Smuzhiyun void do_dw_dma_off(struct dw_dma *dw);
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun int do_dw_dma_disable(struct dw_dma_chip *chip);
22*4882a593Smuzhiyun int do_dw_dma_enable(struct dw_dma_chip *chip);
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun extern bool dw_dma_filter(struct dma_chan *chan, void *param);
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #ifdef CONFIG_ACPI
27*4882a593Smuzhiyun void dw_dma_acpi_controller_register(struct dw_dma *dw);
28*4882a593Smuzhiyun void dw_dma_acpi_controller_free(struct dw_dma *dw);
29*4882a593Smuzhiyun #else /* !CONFIG_ACPI */
dw_dma_acpi_controller_register(struct dw_dma * dw)30*4882a593Smuzhiyun static inline void dw_dma_acpi_controller_register(struct dw_dma *dw) {}
dw_dma_acpi_controller_free(struct dw_dma * dw)31*4882a593Smuzhiyun static inline void dw_dma_acpi_controller_free(struct dw_dma *dw) {}
32*4882a593Smuzhiyun #endif /* !CONFIG_ACPI */
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun struct platform_device;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #ifdef CONFIG_OF
37*4882a593Smuzhiyun struct dw_dma_platform_data *dw_dma_parse_dt(struct platform_device *pdev);
38*4882a593Smuzhiyun void dw_dma_of_controller_register(struct dw_dma *dw);
39*4882a593Smuzhiyun void dw_dma_of_controller_free(struct dw_dma *dw);
40*4882a593Smuzhiyun #else
dw_dma_parse_dt(struct platform_device * pdev)41*4882a593Smuzhiyun static inline struct dw_dma_platform_data *dw_dma_parse_dt(struct platform_device *pdev)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun return NULL;
44*4882a593Smuzhiyun }
dw_dma_of_controller_register(struct dw_dma * dw)45*4882a593Smuzhiyun static inline void dw_dma_of_controller_register(struct dw_dma *dw) {}
dw_dma_of_controller_free(struct dw_dma * dw)46*4882a593Smuzhiyun static inline void dw_dma_of_controller_free(struct dw_dma *dw) {}
47*4882a593Smuzhiyun #endif
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun struct dw_dma_chip_pdata {
50*4882a593Smuzhiyun const struct dw_dma_platform_data *pdata;
51*4882a593Smuzhiyun int (*probe)(struct dw_dma_chip *chip);
52*4882a593Smuzhiyun int (*remove)(struct dw_dma_chip *chip);
53*4882a593Smuzhiyun struct dw_dma_chip *chip;
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun static __maybe_unused const struct dw_dma_chip_pdata dw_dma_chip_pdata = {
57*4882a593Smuzhiyun .probe = dw_dma_probe,
58*4882a593Smuzhiyun .remove = dw_dma_remove,
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun static const struct dw_dma_platform_data idma32_pdata = {
62*4882a593Smuzhiyun .nr_channels = 8,
63*4882a593Smuzhiyun .chan_allocation_order = CHAN_ALLOCATION_ASCENDING,
64*4882a593Smuzhiyun .chan_priority = CHAN_PRIORITY_ASCENDING,
65*4882a593Smuzhiyun .block_size = 131071,
66*4882a593Smuzhiyun .nr_masters = 1,
67*4882a593Smuzhiyun .data_width = {4},
68*4882a593Smuzhiyun .multi_block = {1, 1, 1, 1, 1, 1, 1, 1},
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun static __maybe_unused const struct dw_dma_chip_pdata idma32_chip_pdata = {
72*4882a593Smuzhiyun .pdata = &idma32_pdata,
73*4882a593Smuzhiyun .probe = idma32_dma_probe,
74*4882a593Smuzhiyun .remove = idma32_dma_remove,
75*4882a593Smuzhiyun };
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun #endif /* _DMA_DW_INTERNAL_H */
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