1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates. 4*4882a593Smuzhiyun * Synopsys DesignWare eDMA v0 core 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Author: Gustavo Pimentel <gustavo.pimentel@synopsys.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _DW_EDMA_V0_CORE_H 10*4882a593Smuzhiyun #define _DW_EDMA_V0_CORE_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/dma/edma.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* eDMA management callbacks */ 15*4882a593Smuzhiyun void dw_edma_v0_core_off(struct dw_edma *chan); 16*4882a593Smuzhiyun u16 dw_edma_v0_core_ch_count(struct dw_edma *chan, enum dw_edma_dir dir); 17*4882a593Smuzhiyun enum dma_status dw_edma_v0_core_ch_status(struct dw_edma_chan *chan); 18*4882a593Smuzhiyun void dw_edma_v0_core_clear_done_int(struct dw_edma_chan *chan); 19*4882a593Smuzhiyun void dw_edma_v0_core_clear_abort_int(struct dw_edma_chan *chan); 20*4882a593Smuzhiyun u32 dw_edma_v0_core_status_done_int(struct dw_edma *chan, enum dw_edma_dir dir); 21*4882a593Smuzhiyun u32 dw_edma_v0_core_status_abort_int(struct dw_edma *chan, enum dw_edma_dir dir); 22*4882a593Smuzhiyun void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first); 23*4882a593Smuzhiyun int dw_edma_v0_core_device_config(struct dw_edma_chan *chan); 24*4882a593Smuzhiyun /* eDMA debug fs callbacks */ 25*4882a593Smuzhiyun void dw_edma_v0_core_debugfs_on(struct dw_edma_chip *chip); 26*4882a593Smuzhiyun void dw_edma_v0_core_debugfs_off(void); 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #endif /* _DW_EDMA_V0_CORE_H */ 29