1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
4*4882a593Smuzhiyun * Synopsys DesignWare eDMA PCIe driver
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Author: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/kernel.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/pci.h>
12*4882a593Smuzhiyun #include <linux/device.h>
13*4882a593Smuzhiyun #include <linux/dma/edma.h>
14*4882a593Smuzhiyun #include <linux/pci-epf.h>
15*4882a593Smuzhiyun #include <linux/msi.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include "dw-edma-core.h"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun struct dw_edma_pcie_data {
20*4882a593Smuzhiyun /* eDMA registers location */
21*4882a593Smuzhiyun enum pci_barno rg_bar;
22*4882a593Smuzhiyun off_t rg_off;
23*4882a593Smuzhiyun size_t rg_sz;
24*4882a593Smuzhiyun /* eDMA memory linked list location */
25*4882a593Smuzhiyun enum pci_barno ll_bar;
26*4882a593Smuzhiyun off_t ll_off;
27*4882a593Smuzhiyun size_t ll_sz;
28*4882a593Smuzhiyun /* eDMA memory data location */
29*4882a593Smuzhiyun enum pci_barno dt_bar;
30*4882a593Smuzhiyun off_t dt_off;
31*4882a593Smuzhiyun size_t dt_sz;
32*4882a593Smuzhiyun /* Other */
33*4882a593Smuzhiyun u32 version;
34*4882a593Smuzhiyun enum dw_edma_mode mode;
35*4882a593Smuzhiyun u8 irqs;
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun static const struct dw_edma_pcie_data snps_edda_data = {
39*4882a593Smuzhiyun /* eDMA registers location */
40*4882a593Smuzhiyun .rg_bar = BAR_0,
41*4882a593Smuzhiyun .rg_off = 0x00001000, /* 4 Kbytes */
42*4882a593Smuzhiyun .rg_sz = 0x00002000, /* 8 Kbytes */
43*4882a593Smuzhiyun /* eDMA memory linked list location */
44*4882a593Smuzhiyun .ll_bar = BAR_2,
45*4882a593Smuzhiyun .ll_off = 0x00000000, /* 0 Kbytes */
46*4882a593Smuzhiyun .ll_sz = 0x00800000, /* 8 Mbytes */
47*4882a593Smuzhiyun /* eDMA memory data location */
48*4882a593Smuzhiyun .dt_bar = BAR_2,
49*4882a593Smuzhiyun .dt_off = 0x00800000, /* 8 Mbytes */
50*4882a593Smuzhiyun .dt_sz = 0x03800000, /* 56 Mbytes */
51*4882a593Smuzhiyun /* Other */
52*4882a593Smuzhiyun .version = 0,
53*4882a593Smuzhiyun .mode = EDMA_MODE_UNROLL,
54*4882a593Smuzhiyun .irqs = 1,
55*4882a593Smuzhiyun };
56*4882a593Smuzhiyun
dw_edma_pcie_irq_vector(struct device * dev,unsigned int nr)57*4882a593Smuzhiyun static int dw_edma_pcie_irq_vector(struct device *dev, unsigned int nr)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun return pci_irq_vector(to_pci_dev(dev), nr);
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun static const struct dw_edma_core_ops dw_edma_pcie_core_ops = {
63*4882a593Smuzhiyun .irq_vector = dw_edma_pcie_irq_vector,
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun
dw_edma_pcie_probe(struct pci_dev * pdev,const struct pci_device_id * pid)66*4882a593Smuzhiyun static int dw_edma_pcie_probe(struct pci_dev *pdev,
67*4882a593Smuzhiyun const struct pci_device_id *pid)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun const struct dw_edma_pcie_data *pdata = (void *)pid->driver_data;
70*4882a593Smuzhiyun struct device *dev = &pdev->dev;
71*4882a593Smuzhiyun struct dw_edma_chip *chip;
72*4882a593Smuzhiyun int err, nr_irqs;
73*4882a593Smuzhiyun struct dw_edma *dw;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* Enable PCI device */
76*4882a593Smuzhiyun err = pcim_enable_device(pdev);
77*4882a593Smuzhiyun if (err) {
78*4882a593Smuzhiyun pci_err(pdev, "enabling device failed\n");
79*4882a593Smuzhiyun return err;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /* Mapping PCI BAR regions */
83*4882a593Smuzhiyun err = pcim_iomap_regions(pdev, BIT(pdata->rg_bar) |
84*4882a593Smuzhiyun BIT(pdata->ll_bar) |
85*4882a593Smuzhiyun BIT(pdata->dt_bar),
86*4882a593Smuzhiyun pci_name(pdev));
87*4882a593Smuzhiyun if (err) {
88*4882a593Smuzhiyun pci_err(pdev, "eDMA BAR I/O remapping failed\n");
89*4882a593Smuzhiyun return err;
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun pci_set_master(pdev);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /* DMA configuration */
95*4882a593Smuzhiyun err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
96*4882a593Smuzhiyun if (!err) {
97*4882a593Smuzhiyun err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
98*4882a593Smuzhiyun if (err) {
99*4882a593Smuzhiyun pci_err(pdev, "consistent DMA mask 64 set failed\n");
100*4882a593Smuzhiyun return err;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun } else {
103*4882a593Smuzhiyun pci_err(pdev, "DMA mask 64 set failed\n");
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
106*4882a593Smuzhiyun if (err) {
107*4882a593Smuzhiyun pci_err(pdev, "DMA mask 32 set failed\n");
108*4882a593Smuzhiyun return err;
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
112*4882a593Smuzhiyun if (err) {
113*4882a593Smuzhiyun pci_err(pdev, "consistent DMA mask 32 set failed\n");
114*4882a593Smuzhiyun return err;
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun /* Data structure allocation */
119*4882a593Smuzhiyun chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
120*4882a593Smuzhiyun if (!chip)
121*4882a593Smuzhiyun return -ENOMEM;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun dw = devm_kzalloc(dev, sizeof(*dw), GFP_KERNEL);
124*4882a593Smuzhiyun if (!dw)
125*4882a593Smuzhiyun return -ENOMEM;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun /* IRQs allocation */
128*4882a593Smuzhiyun nr_irqs = pci_alloc_irq_vectors(pdev, 1, pdata->irqs,
129*4882a593Smuzhiyun PCI_IRQ_MSI | PCI_IRQ_MSIX);
130*4882a593Smuzhiyun if (nr_irqs < 1) {
131*4882a593Smuzhiyun pci_err(pdev, "fail to alloc IRQ vector (number of IRQs=%u)\n",
132*4882a593Smuzhiyun nr_irqs);
133*4882a593Smuzhiyun return -EPERM;
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun /* Data structure initialization */
137*4882a593Smuzhiyun chip->dw = dw;
138*4882a593Smuzhiyun chip->dev = dev;
139*4882a593Smuzhiyun chip->id = pdev->devfn;
140*4882a593Smuzhiyun chip->irq = pdev->irq;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun dw->rg_region.vaddr = pcim_iomap_table(pdev)[pdata->rg_bar];
143*4882a593Smuzhiyun dw->rg_region.vaddr += pdata->rg_off;
144*4882a593Smuzhiyun dw->rg_region.paddr = pdev->resource[pdata->rg_bar].start;
145*4882a593Smuzhiyun dw->rg_region.paddr += pdata->rg_off;
146*4882a593Smuzhiyun dw->rg_region.sz = pdata->rg_sz;
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun dw->ll_region.vaddr = pcim_iomap_table(pdev)[pdata->ll_bar];
149*4882a593Smuzhiyun dw->ll_region.vaddr += pdata->ll_off;
150*4882a593Smuzhiyun dw->ll_region.paddr = pdev->resource[pdata->ll_bar].start;
151*4882a593Smuzhiyun dw->ll_region.paddr += pdata->ll_off;
152*4882a593Smuzhiyun dw->ll_region.sz = pdata->ll_sz;
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun dw->dt_region.vaddr = pcim_iomap_table(pdev)[pdata->dt_bar];
155*4882a593Smuzhiyun dw->dt_region.vaddr += pdata->dt_off;
156*4882a593Smuzhiyun dw->dt_region.paddr = pdev->resource[pdata->dt_bar].start;
157*4882a593Smuzhiyun dw->dt_region.paddr += pdata->dt_off;
158*4882a593Smuzhiyun dw->dt_region.sz = pdata->dt_sz;
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun dw->version = pdata->version;
161*4882a593Smuzhiyun dw->mode = pdata->mode;
162*4882a593Smuzhiyun dw->nr_irqs = nr_irqs;
163*4882a593Smuzhiyun dw->ops = &dw_edma_pcie_core_ops;
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun /* Debug info */
166*4882a593Smuzhiyun pci_dbg(pdev, "Version:\t%u\n", dw->version);
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun pci_dbg(pdev, "Mode:\t%s\n",
169*4882a593Smuzhiyun dw->mode == EDMA_MODE_LEGACY ? "Legacy" : "Unroll");
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun pci_dbg(pdev, "Registers:\tBAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n",
172*4882a593Smuzhiyun pdata->rg_bar, pdata->rg_off, pdata->rg_sz,
173*4882a593Smuzhiyun dw->rg_region.vaddr, &dw->rg_region.paddr);
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun pci_dbg(pdev, "L. List:\tBAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n",
176*4882a593Smuzhiyun pdata->ll_bar, pdata->ll_off, pdata->ll_sz,
177*4882a593Smuzhiyun dw->ll_region.vaddr, &dw->ll_region.paddr);
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun pci_dbg(pdev, "Data:\tBAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n",
180*4882a593Smuzhiyun pdata->dt_bar, pdata->dt_off, pdata->dt_sz,
181*4882a593Smuzhiyun dw->dt_region.vaddr, &dw->dt_region.paddr);
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun pci_dbg(pdev, "Nr. IRQs:\t%u\n", dw->nr_irqs);
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun /* Validating if PCI interrupts were enabled */
186*4882a593Smuzhiyun if (!pci_dev_msi_enabled(pdev)) {
187*4882a593Smuzhiyun pci_err(pdev, "enable interrupt failed\n");
188*4882a593Smuzhiyun return -EPERM;
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun dw->irq = devm_kcalloc(dev, nr_irqs, sizeof(*dw->irq), GFP_KERNEL);
192*4882a593Smuzhiyun if (!dw->irq)
193*4882a593Smuzhiyun return -ENOMEM;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun /* Starting eDMA driver */
196*4882a593Smuzhiyun err = dw_edma_probe(chip);
197*4882a593Smuzhiyun if (err) {
198*4882a593Smuzhiyun pci_err(pdev, "eDMA probe failed\n");
199*4882a593Smuzhiyun return err;
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun /* Saving data structure reference */
203*4882a593Smuzhiyun pci_set_drvdata(pdev, chip);
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun return 0;
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun
dw_edma_pcie_remove(struct pci_dev * pdev)208*4882a593Smuzhiyun static void dw_edma_pcie_remove(struct pci_dev *pdev)
209*4882a593Smuzhiyun {
210*4882a593Smuzhiyun struct dw_edma_chip *chip = pci_get_drvdata(pdev);
211*4882a593Smuzhiyun int err;
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun /* Stopping eDMA driver */
214*4882a593Smuzhiyun err = dw_edma_remove(chip);
215*4882a593Smuzhiyun if (err)
216*4882a593Smuzhiyun pci_warn(pdev, "can't remove device properly: %d\n", err);
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun /* Freeing IRQs */
219*4882a593Smuzhiyun pci_free_irq_vectors(pdev);
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun static const struct pci_device_id dw_edma_pcie_id_table[] = {
223*4882a593Smuzhiyun { PCI_DEVICE_DATA(SYNOPSYS, EDDA, &snps_edda_data) },
224*4882a593Smuzhiyun { }
225*4882a593Smuzhiyun };
226*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, dw_edma_pcie_id_table);
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun static struct pci_driver dw_edma_pcie_driver = {
229*4882a593Smuzhiyun .name = "dw-edma-pcie",
230*4882a593Smuzhiyun .id_table = dw_edma_pcie_id_table,
231*4882a593Smuzhiyun .probe = dw_edma_pcie_probe,
232*4882a593Smuzhiyun .remove = dw_edma_pcie_remove,
233*4882a593Smuzhiyun };
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun module_pci_driver(dw_edma_pcie_driver);
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
238*4882a593Smuzhiyun MODULE_DESCRIPTION("Synopsys DesignWare eDMA PCIe driver");
239*4882a593Smuzhiyun MODULE_AUTHOR("Gustavo Pimentel <gustavo.pimentel@synopsys.com>");
240